Bilayer graphene tunneling field effect transistor
A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.
1. A bilayer graphene tunnelling field effect transistor, comprising:
a bilayer graphene having a bottom surface and a top surface;
a bottom gate electrode capacitively coupled to the bottom surface of the bilayer graphene;
a first top gate electrode capacitively coupled to the top surface of the graphene bilayer; and
a second top gate electrode capacitively coupled to the top surface of the bilayer graphene and spaced apart along the top surface from the first top gate electrode, whereby the bottom gate electrode fully overlaps the first top gate electrode and the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode, a barrier region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the bottom gate electrode.
2. The bilayer graphene tunnelling field effect transistor of claim 1 , further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
3. The bilayer graphene tunnelling field effect transistor of claim 1 , wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
4. A bilayer graphene tunnelling field effect transistor, comprising:
a bilayer graphene having a bottom surface and a top surface;
a bottom gate electrode capacitively coupled to the bottom surface of the bilayer graphene; and
a first top gate electrode capacitively coupled to the top surface of the graphene bilayer,
wherein the bottom gate electrode at least partially overlaps the first top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region only capacitively coupled to the top gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein the top gate electrode is covered by a top dielectric layer and wherein the drain region is sandwiched in between the bottom gate electrode and a part of the top dielectric layer.
5. The bilayer graphene tunnelling field effect transistor of claim 1 , further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
6. The bilayer graphene tunnelling field effect transistor of claim 2 , wherein the first and second gate dielectric layers have a same equivalent oxide thickness.
7. The bilayer graphene tunneling field effect transistor of claim 2 , further comprising a second top gate electrode capacitively coupled to the top surface of the bilayer graphene and spaced apart along the top surface from the first top gate electrode, wherein the bottom gate electrode fully overlaps the first top gate electrode and the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode, a barrier region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein the transistor comprises a first top gate electrode and a second top gate electrode and wherein both the first top gate electrode and the second top gate electrode contact the second gate dielectric layer opposite to the second graphene layer.
8. The bilayer graphene tunnelling field effect transistor of claim 1 , wherein the bilayer graphene layer is chemically undoped.
9. A bilayer graphene tunnelling field effect transistor, comprising:
a bilayer graphene having a bottom surface and a top surface;
a bottom gate electrode capacitively coupled to the bottom surface of the bilayer graphene; and
a first top gate electrode capacitively coupled to the top surface of the graphene bilayer,
wherein the bottom gate electrode at least partially overlaps the first top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region only capacitively coupled to the top gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein a p-i-n junction or n-i-p junction is electrostatically induced in the bilayer graphene.
10. The bilayer graphene tunneling field effect transistor of claim 9 , wherein the p-i-n junction or an n-i-p junction is electrostatically induced by applying a voltage to a top gate electrode and a voltage of opposite sign to the bottom gate electrode.
11. The bilayer graphene tunneling field effect transistor of claim 1 , wherein a p-i-n junction or n-i-p junction is electrostatically induced in the bilayer graphene.
12. The bilayer graphene tunneling field effect transistor of claim 11 , wherein the p-n-i-n junction or n-p-i-p junction is electrostatically induced by applying a constant bias Vbg to the bottom gate electrode, applying a bias Vtg 2 of opposite sign to Vbg, wherein |Vtg 2 |>|Vbg|, to the second top gate electrode to create the p-type source region, and applying a voltage Vtg 1 of opposite sign to Vbg to the first top gate electrode to create an intrinsic channel region in the bilayer graphene, wherein |Vtg 1 | is substantially equal to |Vbg| when measured in absence of applied drain-source voltage V ds .
13. The bilayer graphene tunnelling field effect transistor of claim 4 , further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
14. The bilayer graphene tunnelling field effect transistor of claim 4 , wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
15. The bilayer graphene tunnelling field effect transistor of claim 4 , further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
16. The bilayer graphene tunnelling field effect transistor of claim 4 , wherein the bilayer graphene layer is chemically undoped.
17. The bilayer graphene tunnelling field effect transistor of claim 9 , further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
18. The bilayer graphene tunnelling field effect transistor of claim 9 , wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
19. The bilayer graphene tunnelling field effect transistor of claim 9 , further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
20. The bilayer graphene tunnelling field effect transistor of claim 9 , wherein the bilayer graphene layer is chemically undoped.