Method of forming stacked trench contacts and structures formed thereby

1. A transistor on a substrate comprising:

a gate structure comprising a gate electrode layer, the gate electrode having a top surface;

a source region on a first side of the gate structure;

a first spacer on the first side of the gate structure and in direct contact with the gate structure;

a first silicide layer on a top surface of the source region, wherein the first silicide layer does not extend below the first spacer;

a drain region on a second side of the gate structure;

a second spacer on the second side of the gate structure and in direct contact with the gate structure;

a second silicide layer on a top surface of the drain region, wherein the second silicide layer does not extend below the second spacer;

a first ILD on the first side and the second side of the gate structure and having a top surface which is coplanar with the top surface of the gate electrode;

a second ILD layer over the first ILD layer;

a first contact metal in the first ILD layer coupled to the first silicide layer;

a second contact metal within the second ILD layer that is directly coupled to the first contact metal, wherein the second contact metal comprises a tapered structure having a bottom portion that is smaller in width than a top portion of the second contact metal;

a third contact metal in the first ILD layer coupled to the second silicide layer; and

a fourth contact metal within the second ILD layer that is directly coupled to the third contact metal, wherein the fourth contact metal comprises a tapered structure having a bottom portion that is smaller in width than a top portion of the fourth contact metal.

2. The transistor of claim 1 , wherein the second contact metal further comprises having a bottom portion that is smaller in width than a top portion of the first contact metal.

3. The transistor of claim 1 , wherein the fourth contact metal further comprises having a bottom portion that is smaller in width than a top portion of the third contact metal.

4. The transistor of claim 1 , wherein gate electrode layer comprises hafnium, zirconium, titanium, tantalum, or aluminum.

5. The transistor of claim 1 , wherein the substrate comprises silicon, silicon-on-insulator, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

6. The transistor of claim 1 , wherein the first and second spacers comprise silicon dioxide or silicon nitride.

7. The transistor of claim 1 , wherein the first and second silicide layers comprise nickel salicide.

8. A method of forming a transistor on a substrate comprising:

forming a gate structure comprising a gate electrode layer on the substrate;

forming a source region on a first side of the gate structure;

forming a first spacer on the first side of the gate structure and in direct contact with the gate structure;

forming a drain region on a second side of the gate structure;

forming a second spacer on the second side of the gate structure and in direct contact with the gate structure;

forming a first ILD layer over the transistor;

etching a first trench contact opening in the first ILD layer to expose at least a portion of the source region;

through the first trench contact opening, forming a first salicide layer on a top surface of the source region;

filling the first trench contact opening with a metal to form a first trench contact;

etching a second trench contact opening in the first ILD layer that exposes at least a portion of the drain region;

through the second trench contact opening, forming a second salicide layer on a top portion of the drain region;

filling the second trench contact opening with a metal to form a second trench contact;

forming a second ILD layer over the first ILD layer;

etching a third trench contact opening in the second ILD layer that exposes at least a portion of the first trench contact, wherein the third trench contact opening has a tapered shape so that a bottom portion of the third trench contact opening is smaller in width than a top portion of the third trench contact opening;

filling the third trench contact opening with a metal to form a third trench contact;

etching a fourth trench contact opening in the second ILD layer that exposes at least a portion of the second trench contact, wherein the fourth trench contact opening has a tapered shape so that a bottom portion of the fourth trench contact opening is smaller in width than a top portion of the fourth trench contact opening; and

filling the fourth trench contact opening with a metal to form a fourth trench contact.

9. The method of claim 8 , wherein the third trench contact opening further has a bottom portion that is smaller in width than a top portion of the first trench contact.

10. The method of claim 8 , wherein the fourth trench contact opening further has a bottom portion that is smaller in width than a top portion of the second trench contact.

11. The method of claim 8 , wherein gate electrode layer comprises hafnium, zirconium, titanium, tantalum, or aluminum.

12. The method of claim 8 , wherein the substrate comprises silicon, silicon-on-insulator, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

13. The method of claim 8 , wherein the first and second spacers comprise silicon dioxide or silicon nitride.

14. The method of claim 8 , wherein the first and second silicide layers comprise nickel salicide.