Voltage regulator
A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
1. A voltage regulator circuit comprising:
an amplifier having an inverting input and a non-inverting input, the amplifier being configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier;
an output node;
a first power node;
a second power node;
a driver configured to generate a driving current flowing toward the output node in response to the control signal, the driver being coupled between the first power node and the output node;
a first transistor having a gate, the first transistor being coupled between the output node and the second power node; and
a bias circuit outside the amplifier configured to supply a bias signal to the gate of the first transistor, the first transistor being configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
2. The voltage regulator circuit of claim 1 , wherein the bias circuit comprises a second transistor and a current source circuit connected to a gate and a drain of the second transistor, a source of the second transistor is connected to a ground, and the drain of the second transistor is connected to the gate of the first transistor through a resistor.
3. The voltage regulator circuit of claim 2 , wherein the first transistor is an NMOS transistor and the second transistor is an NMOS transistor.
4. The voltage regulator circuit of claim 3 , wherein the first transistor is adjustable to change a current capacity of the first transistor.
5. The voltage regulator circuit of claim 2 , wherein a capacitor is connected to the output node and to the ground.
6. The voltage regulator circuit of claim 2 , wherein the current source circuit includes a variable resistor connected to the second power node.
7. The voltage regulator circuit of claim 1 , wherein the amplifier further comprises an amplifier output connected to the gate of the first transistor through a capacitor.
8. A voltage regulator circuit comprising:
an output node;
a feedback loop;
a first transistor having a first gate, the first transistor being configured to generate a first driving current flowing toward the output node in response to at least a reference voltage and a voltage level at the output node, the first gate of the first transistor and the output node being within the feed-back loop;
a second transistor having a second gate, the second transistor being configured to generate a second driving current flowing away from the output node, the second gate of the second transistor being outside of the feed-back loop; and
a bias circuit configured to supply a bias signal to the second gate of the second transistor, the second transistor being configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
9. The voltage regulator circuit of claim 8 , wherein the bias circuit comprises a third transistor and a current source circuit connected to a gate and a drain of the third transistor, a source of the third transistor is connected to a ground, and the drain of the third transistor is connected to the second gate of the second transistor through a resistor.
10. The voltage regulator circuit of claim 9 , wherein the second transistor is an NMOS transistor and the third transistor is an NMOS transistor.
11. The voltage regulator circuit of claim 10 , wherein the second transistor is adjustable to change a current capacity of the second transistor.
12. The voltage regulator circuit of claim 9 , wherein a capacitor is connected to the output node and to the ground.
13. The voltage regulator circuit of claim 9 , wherein the current source circuit includes a variable resistor connected to the second power node.
14. The voltage regulator circuit of claim 8 , wherein the first transistor is connected to the second gate of the second transistor through a capacitor.
15. A voltage regulator circuit comprising:
an amplifier having an inverting input, a non-inverting input, a first output and a second output, the amplifier being configured to generate a first control signal based on a reference signal at the inverting input of the amplifier, output the first control signal at the first output of the amplifier, generate a second control signal based on a feedback signal at the non-inverting input of the amplifier, and output the second control signal at the second output of the amplifier;
a first power node;
a second power node;
a driver configured to generate a driving current flowing toward the output node in response to the first control signal, the driver being coupled between the first power node and the output node;
a first transistor having a gate, the first transistor being coupled between the output node and the second power node, and the second control signal being AC coupled with the gate of the first transistor; and
a bias circuit outside the amplifier configured to cause the first transistor to be DC biased by supplying a bias signal to the gate of the first transistor,
wherein the first transistor is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
16. The voltage regulator circuit of claim 15 , wherein the bias circuit comprises a second transistor and a current source circuit connected to a gate and a drain of the second transistor, wherein a source of the second transistor is connected to a ground and the drain of the second transistor is connected to the gate of the first transistor through a resistor.
17. The voltage regulator circuit of claim 16 , wherein the first transistor is an NMOS transistor and the second transistor is an NMOS transistor.
18. The voltage regulator circuit of claim 17 , wherein the first transistor is adjustable to change a current capacity of the first transistor.
19. The voltage regulator circuit of claim 16 , wherein a capacitor is connected to the output node and to the ground.
20. The voltage regulator circuit of claim 16 , wherein the current source circuit includes a variable resistor connected to the second power node.