Asynchronous lookahead hierarchical branch prediction

1. A system for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer, the system comprising:

a first-level branch target buffer;

a second-level branch target buffer;

a lookaside buffer; and

a branch prediction and eviction logic processing circuit coupled to the first-level branch target buffer, the second-level branch target buffer, and the lookaside buffer, the processing circuit configured to perform:

receiving a search request to locate branch prediction information associated with a search address;

searching, by the processing circuit, for an entry corresponding to the search request in the first-level branch target buffer;

based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate a plurality of entries in the second-level branch target buffer having a memory region corresponding to the search request;

determining priority information based on the lookaside buffer that tracks a program execution path indicating locations of the second-level branch target buffer referenced as executed code and indicating locations that were unreferenced as executed code during program execution in a plurality of sub-blocks of a block of entries in the second-level branch target buffer, wherein the lookaside buffer further tracks references between a plurality of segments of the block, wherein the segments group the sub-blocks, and further wherein the lookaside buffer indicates which of the segments were transitioned to and which of the segments of were not transitioned to by each of the segments of the block; and

based on locating the entries in the second-level branch target buffer, performing the bulk transfer of the entries from the second-level branch target buffer to the first-level branch target buffer as a sequence of transfers for the block of entries based on the priority information as applied across the segments of the sub-blocks in transferring both the locations that were referenced and the locations were unreferenced from the block of the second-level branch target buffer.

2. The system of claim 1 , wherein initiating the secondary search is based on failing to locate the matching entry in the first-level branch target buffer for a predetermined number of searches since one or more of: a previous prediction, a surprise branch, and a restart.

3. The system of claim 1 , wherein the processing circuit is further configured to perform:

using a tracker to manage the secondary search and control the bulk transfer, wherein the bulk transfer returns the entries from the second-level branch target buffer to one or more of: the first-level branch target buffer and a branch target buffer preload table; and

maintaining a recently completed search history comprising a list of recently completed searches of the second-level branch target buffer.

4. The system of claim 3 , wherein the processing circuit is further configured to perform:

prior to creating a new tracker for a new secondary search, checking the recently completed search history to confirm that the new secondary search does not match one of the recently completed searches; and

prior to creating the new tracker for the new secondary search, checking other trackers to confirm that the new secondary search does not match an active secondary search.

5. The system of claim 1 , wherein the processing circuit is further configured to perform:

transferring with a highest priority, a demand sub-block that initiated the secondary search;

transferring with a second highest priority, referenced sub-blocks in a same segment as the demand sub-block;

transferring with a third highest priority, referenced sub-blocks in other segments of the block;

transferring with a fourth highest priority, sub-blocks with no available reference information; and

transferring with a lowest priority, unreferenced sub-blocks.

6. The system of claim 1 , wherein the processing circuit is further configured to perform:

transferring with a highest priority, a demand sub-block that initiated the secondary search;

transferring with a second highest priority, referenced sub-blocks in a same segment as the demand sub-block;

transferring with a third highest priority, referenced sub-blocks in referenced segments of the block;

transferring with a fourth highest priority, referenced sub-blocks in unreferenced segments of the block;

transferring with a fifth highest priority, sub-blocks with no available reference information; and

transferring with a lowest priority, unreferenced sub-blocks.

7. The system of claim 1 , wherein the priority information is associated with a plurality of priority levels, and the processing circuit is further configured to perform:

managing multiple bulk transfers using trackers; and

interleaving transfers for the trackers on a priority-level basis to transfer the sub-blocks at a same higher priority level across the trackers prior to transferring the sub-blocks at a same lower priority level across the trackers.