Compositional graded IGZO thin film transistor
A gradient in the composition of at least one of the elements of a metal-based semiconductor layer is introduced as a function of depth through the layer. The gradient(s) influence the current density response of the device at different gate voltages. In some embodiments, the composition of an element (e.g. Ga) is greater at the interface between the metal-based semiconductor layer and the source/drain layers. The shape of the gradient profile is one of linear, stepped, parabolic, exponential, and the like.
1. A method comprising:
providing a substrate;
forming a metal-based semiconductor layer above a surface of the substrate,
wherein the metal-based semiconductor layer comprises two or more elements;
wherein the metal-based semiconductor layer has a lower surface and an upper surface, and
wherein at least one element of the metal-based semiconductor layer is varied in concentration from the lower surface to the upper surface during the forming.
2. The method of claim 1 , wherein the metal-based semiconductor layer comprises indium, gallium, zinc, and oxygen.
3. The method of claim 1 , wherein the metal-based semiconductor layer is operable as a semiconductor layer in a thin film transistor device, and further comprising:
forming a gate electrode layer above the surface of the substrate, wherein the metal-based semiconductor layer is formed above the gate electrode;
forming a gate dielectric layer above the gate electrode layer, wherein the metal-based semiconductor layer is formed above the gate dielectric layer; and
forming a source electrode and a drain electrode above the metal-based semiconductor layer.
4. The method of claim 3 , wherein the metal-based semiconductor layer is formed using a deposition technique, the deposition technique comprising least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and evaporation, and further comprising varying a deposition parameter of the deposition technique during the forming of the metal-based semiconductor layer.
5. The method of claim 1 , wherein the deposition technique comprises PVD, and the deposition parameter comprises at least one of a composition of sputter targets, a power supplied to the sputter targets, a gaseous pressure within a PVD chamber in which the PVD occurs, a flow rate of gas within the PVD chamber, a composition of the gas within the PVD chamber, a distance between the sputter targets and the substrate, a flow rate, or a combination thereof.
6. The method of claim 1 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium is lower at the lower surface of the metal-based semiconductor layer.
7. The method of claim 1 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in a linear manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
8. The method of claim 1 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in a stepped manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
9. The method of claim 1 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in a parabolic manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
10. The method of claim 1 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in an exponential manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
11. A thin film transistor device comprising:
a substrate;
a metal-based semiconductor layer above a surface of the substrate,
wherein the metal-based semiconductor layer comprises two or more elements;
wherein the metal-based semiconductor layer has a lower surface and an upper surface, and
wherein at least one element of the metal-based semiconductor layer varies in concentration from the lower surface to the upper surface of the metal-based semiconductor layer.
12. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer comprises indium, gallium, zinc, and oxygen.
13. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer is operable as a semiconductor layer in the thin film transistor device.
14. The thin film transistor device of claim 13 , wherein the thin film transistor device is operable as a transistor in a display device.
15. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium is lower at the lower surface of the metal-based semiconductor layer.
16. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in a linear manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
17. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in a stepped manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
18. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in a parabolic manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
19. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer comprises gallium and a concentration of the gallium varies in an exponential manner from the lower surface of the metal-based semiconductor layer to the upper surface of the metal-based semiconductor layer.
20. The thin film transistor device of claim 11 , wherein the metal-based semiconductor layer is deposited by one of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).