IP Library Granted Patent US 9,299,623
Granted Patent B2
US 9,299,623 · App. 13/671,902 · Granted Mar 29, 2016

Run-to-run control utilizing virtual metrology in semiconductor manufacturing

Inventors: Robert J. Baseman (Brewster, NY); Jingrui He (Yorktown Heights, NY); Emmanuel Yashchin (Yorktown Heights, NY); Yada Zhu (White Plains, NY)
Assignee: International Business Machines Corporation
H01L22/20G05B13/048G05B19/41875G05B2219/32182G05B2219/32187G05B2219/32194G05B2219/45031Y02P90/22
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Quick Facts
Patent No.
US 9,299,623
App. No.
13/671,902
Granted
Mar 29, 2016
Kind
B2
Abstract

An apparatus for performing run-to-run control and sampling optimization in a semiconductor manufacturing process includes at least one control module. The control module is operative: to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; and to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error.

Claims (55)

1. An apparatus for performing run-to-run control and sampling optimization in a semiconductor manufacturing process, the apparatus comprising:

at least one control module operative: to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error; to obtain a prediction model associated with the semiconductor manufacturing process, the prediction model being adapted to predict the process output by estimating at least one processing parameter for the semiconductor manufacturing process; and to perform virtual metrology based on the prediction model, the prediction error being determined as a function of an output of the virtual metrology;

wherein the prediction model comprises a wafer quality prediction model for metrology variable prediction which utilizes tensor input process variables by directly operating on the tensor input process variables.

2. The apparatus of claim 1 , wherein the at least one control module is further operative: to measure at least one target processing parameter corresponding to a wafer fabricated in the current processing run; to compare the measured at least one target processing parameter with an expected value for the at least one target processing parameter; and to determine the metrology error as a function of a variation between the measured at least one target processing parameter and the expected value for the at least one target processing parameter.

3. The apparatus of claim 1 , wherein the prediction model comprises at least one of a single processing chamber based model, a global model across a plurality of processing chambers, a metrology-based prediction model, and a metrology and error-adaptive model.

4. The apparatus of claim 3 , wherein the global model is generated by approximating coefficients corresponding to different processing chambers to a common vector given by prior information on tool capability matching, adding a positive coefficient to balance different terms in the global model, and minimizing the prediction error and optimizing the approximation.

5. The apparatus of claim 4 , wherein the at least one control module is operative to use a block coordinate based algorithm for optimizing the approximation.

6. The apparatus of claim 3 , wherein, in constructing the metrology-based prediction model, the at least one control module is operative: to obtain a plurality of predictors, the predictors comprising information relating to the semiconductor manufacturing process; to decompose the predictors into at least two types, a first type comprising variance profiles, and a second type obtained based on dynamic regression models; and to generate a combined predictor comprising at least a subset of the first type of predictors and at least a subset of the second type of predictors.

7. The apparatus of claim 1 , wherein the at least one control module is further operative: to assign a first weight to the metrology error and a second weight to the prediction error, the first and second weights being indicative of a confidence in the metrology error and prediction error, respectively; and to control the at least one parameter corresponding to a subsequent processing run as a function of the first and second weights.

8. The apparatus of claim 7 , wherein the first and second weights are dynamically adjusted in accordance with a confidence in the metrology error and prediction error, respectively, over time.

9. The apparatus of claim 7 , wherein each of the first and second weights is a percentage, with a sum of the first and second weights being equal to one.

10. The apparatus of claim 7 , wherein the at least one control module is further operative to optimize a sampling policy corresponding to the semiconductor manufacturing process as a function of the first and second weights.

11. The apparatus of claim 7 , wherein respective values of the first and second weights are determined as a function of one or more factors related to uncertainty and chamber matching capabilities associated with the semiconductor manufacturing process.

12. An apparatus for performing run-to-run control and sampling optimization in a semiconductor manufacturing process, the apparatus comprising:

at least one control module operative: to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error; to assign a first weight to the metrology error and a second weight to the prediction error, the first and second weights being indicative of a confidence in the metrology error and prediction error, respectively; to control the at least one parameter corresponding to a subsequent processing run as a function of the first and second weights; and to optimize a sampling policy corresponding to the semiconductor manufacturing process as a function of the first and second weights;

wherein the at least one control module is further operative to optimize the sampling policy by minimizing a sampling frequency of the semiconductor manufacturing process, the sampling frequency being indicative of at least one of a number of processing runs and a number of wafers between consecutive metrology measurements obtained during actual metrology.

13. An apparatus for performing run-to-run control and sampling optimization in a semiconductor manufacturing process, the apparatus comprising:

at least one control module operative: to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error; to assign a first weight to the metrology error and a second weight to the prediction error, the first and second weights being indicative of a confidence in the metrology error and prediction error, respectively; to control the at least one parameter corresponding to a subsequent processing run as a function of the first and second weights; and to optimize a sampling policy corresponding to the semiconductor manufacturing process as a function of the first and second weights;

wherein the at least one control module is further operative to optimize the sampling policy by maximizing a time between actual metrology measurements obtained in connection with the semiconductor manufacturing process.

14. An apparatus for performing run-to-run control and sampling optimization in a semiconductor manufacturing process, the apparatus comprising:

at least one control module operative: to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process; to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error; to assign a first weight to the metrology error and a second weight to the prediction error, the first and second weights being indicative of a confidence in the metrology error and prediction error, respectively; and to control the at least one parameter corresponding to a subsequent processing run as a function of the first and second weights;

wherein the at least one control module is further operative to calculate a given one of the first and second weights according to an expression

α

(

ɛ

)

=

[

ɛ

-

1

T

max

(

ɛ

-

m

T

)

]

2

,

 where α(ε) represents the given one of the first and second weights, ε −1 T represents a prediction error corresponding to a most recent actual metrology, and max (|ε −m T |)represents maximum absolute prediction error among the last m wafers, m being an integer.

15. A computer program product for performing run-to-run control and sampling optimization in a semiconductor manufacturing process, said computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, said computer readable program code comprising:

computer readable program code configured to determine a process output and corresponding metrology error associated with an actual metrology for a current processing run in the semiconductor manufacturing process;

computer readable program code configured to determine a predicted process output and corresponding prediction error associated with a virtual metrology for the current processing run; computer readable program code configured to control at least one parameter corresponding to a subsequent processing run as a function of the metrology error and the prediction error;

computer readable program code configured to obtain a prediction model associated with the semiconductor manufacturing process, the prediction model being adapted to predict the process output by estimating at least one processing parameter for the semiconductor manufacturing process; and

computer readable program code configured to perform virtual metrology based on the prediction model, the prediction error being determined as a function of an output of the virtual metrology;

wherein the prediction model comprises a wafer quality prediction model for metrology variable prediction which utilizes tensor input process variables by directly operating on the tensor input process variables.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2012
From: BASEMAN, ROBERT J.; HE, JINGRUI; YASHCHIN, EMMANUEL; ZHU, YADA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 029264/0277 →
Continuity (2)
Continuation 13557955 · Jul 25, 2012
Related Publication 20140031969A1 · Jan 30, 2014