Controlled solder-on-die integrations on packages and methods of assembling same

1. A process of bumping a die backside, comprising:

opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, the die including an active surface and a backside surface;

filling the recess with a conductive material that contacts the TSV contact; and

forming added solder to the conductive material at a level of the DBF, further including embedding the die in a coreless, bumpless build-up layer (BBUL-C) substrate, wherein the backside surface is exposed and the active surface is coupled to the BBUL-C substrate.

2. The process of claim 1 , further including

removing the DBF.

3. The process of claim 1 , further including:

removing the DBF; and

coupling a subsequent die to the embedded die at the added solder.

4. The process of claim 1 , further including:

removing the DBF;

coupling a subsequent die to the embedded die at the added solder; and

underfilling a material between the subsequent die and the embedded die by capillary underfill (CUF) action.

5. The process of claim 1 , further including:

removing the DBF;

coupling a subsequent die to the embedded die at the added solder; and

underfilling a material between the subsequent die and the embedded die by epoxy flux action.

6. A process of bumping a die backside, comprising:

opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, the die including an active surface and a backside surface;

filling the recess with a conductive material that contacts the TSV contact; and

forming added solder to the conductive material at a level of the DBF, wherein the DBF has a first thickness, wherein the die is a first die, and the process further including:

coupling a subsequent die to the first die by seating the subsequent die upon the DBF such that the first thickness creates a selected offset between the first die and the subsequent die.

7. The process of claim 6 , further including:

removing the DBF; and

underfilling a material between the subsequent die and the first die by capillary underfill (CUF) action.

8. The process of claim 6 , wherein the DBF has a first thickness, wherein the die is a first die, and the process further including:

removing the DBF; and

underfilling a material between the subsequent die and the first die by epoxy flux action.

9. A process of bumping a die backside, comprising:

opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, the die including an active surface and a backside surface;

filling the recess with a conductive material that contacts the TSV contact; and

forming added solder to the conductive material at a level of the DBF, wherein the DBF has a first thickness, the process further including:

removing the DBF; and

underfilling an underfill material to contact at least one of the the conductive material and the added material.

10. The process of claim 9 , the process further including:

removing a fraction of the DBF; and

underfilling an underfill material to contact at least one of the conductive material and the added material.

11. An apparatus comprising:

a die including a through-silicon via (TSV) disposed therein, the die including an active surface and a backside surface;

a TSV contact that contacts the TSV;

a die backside film (DBF) disposed on the backside surface;

a recess that exposes the TSV contact;

conductive material disposed in the recess that contacts the TSV contact; and

added solder that contacts the conductive material, wherein the added solder is disposed at a level of the DBF, wherein the die is an embedded die that is embedded in a coreless, bumpless build-up layer (BBUL-C) substrate, the apparatus further including a subsequent die coupled to the added solder.

12. The apparatus of claim 11 , wherein the subsequent die is seated on the DBF.

13. The apparatus of claim 11 , wherein the die is a first die, that apparatus further including a subsequent die coupled to the added solder, wherein the first die is a logic die with a first pin-out pitch, wherein the subsequent die is a logic die with a subsequent pin-out pitch, and wherein the first pin-out pitch matches the subsequent pin-out pitch.

14. The apparatus of claim 11 , wherein the die is a first die, the apparatus further including a subsequent die coupled to the added solder, wherein the first die is a logic die with a first pin-out pitch, wherein the subsequent die is a memory die with a subsequent pin-out pitch, and wherein the first pin-out pitch is different from the subsequent pin-out pitch.

15. The apparatus of claim 11 , wherein the die is an embedded die that is embedded in a coreless, bumpless build-up layer (BBUL-C) substrate, the apparatus further including:

a subsequent die coupled to the added solder, and wherein the embedded die and the subsequent die are coupled by:

the TSV contact;

the conductive material contacting the TSV contact;

the added solder contacting the conductive material;

an electrical bump coupled to the subsequent die;

and a subsequent die bond pad that contacts the electrical bump.

16. The apparatus of claim 11 , wherein the die is embedded in a coreless, bumpless build-up layer (BBUL-C) substrate, wherein the backside surface is exposed and the active surface is coupled to the BBUL-C substrate to achieve an embedded die.

17. An apparatus comprising:

a die including a through-silicon via (TSV) disposed therein, the die including an active surface and a backside surface;

a TSV contact that contacts the TSV;

an underfill material that contacts the backside surface with a contour characteristic of a removed die backside film (DBF) that was disposed on the backside surface;

conductive material with a contour that is characteristic of having been disposed in a recess of a removed die backside film (DBF), wherein the conductive material contacts the TSV contact; and

added solder that contacts the conductive material.

18. The apparatus of claim 17 , wherein the die is an embedded die that is embedded in a coreless, bumpless build-up layer (BBUL-C) substrate, the apparatus further including a subsequent die coupled to the added solder.

19. The apparatus of claim 17 , wherein the die is a first die, the apparatus further including a subsequent die coupled to the added solder, wherein the first die is a logic die with a first pin-out pitch, wherein the subsequent die is a logic die with a subsequent pin-out pitch, and wherein the first pin-out pitch matches the subsequent pin-out pitch.

20. The apparatus of claim 17 , wherein the die is a first die, the apparatus further including a subsequent die coupled to the added solder, wherein the first die is a logic die with a first pin-out pitch, wherein the subsequent die is a memory die with a subsequent pin-out pitch, and wherein the first pin-out pitch is different from the subsequent pin-out pitch.

21. The apparatus of claim 17 , wherein the die is an embedded die that is embedded in a coreless, bumpless build-up layer (BBUL-C) substrate, the apparatus further including:

a subsequent die coupled to the added solder, and wherein the embedded die and the subsequent die are coupled by:

the TSV contact;

the conductive material contacting the TSV contact;

the added solder contacting the conductive material;

an electrical bump coupled to the subsequent die;

and a subsequent die bond pad that contacts the electrical bump.

22. A computer system comprising:

a die including a through-silicon via (TSV) disposed therein, the die including an active surface and a backside surface;

a TSV contact that contacts the TSV;

an underfill material that contacts the backside surface with a contour characteristic of a removed die backside film (DBF) that was disposed on the backside surface;

conductive material with a contour that is characteristic of having been disposed in a recess of a removed die backside film (DBF), wherein the conductive material contacts the TSV contact;

added solder that contacts the conductive material, wherein the die is an embedded die that is embedded in a coreless, bumpless build-up layer (BBUL-C) substrate, the apparatus further including a subsequent die coupled to the added solder; and

a foundation substrate that supports the semiconductive substrate.

23. The computer system of claim 22 , wherein the foundation substrate is part of a device selected from the group consisting of mobile device, a smartphone device, a tablet computer device, a vehicle, and a television.