IP Library › Granted Patent US 9,299,848
Granted Patent B2
US 9,299,848 · App. 14/645,547 · Granted Mar 29, 2016

Semiconductor device, RF tag, and electronic device

Inventor: Kiyoshi Kato (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78648H01L27/1156H01L27/11551H01L27/1225H01L29/7869H01L29/78651
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Quick Facts
Patent No.
US 9,299,848
App. No.
14/645,547
Granted
Mar 29, 2016
Kind
B2
Abstract

A semiconductor device with a reduced area is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first conductor and a second conductor arranged with a distance therebetween, a first insulator over the first conductor and the second conductor, a semiconductor over the first insulator, a second insulator over the semiconductor, a third conductor over the second insulator, and a fourth conductor and a fifth conductor that are in contact with the semiconductor. The first conductor includes a region not overlapping with the third conductor with the semiconductor therebetween, the first conductor includes a region overlapping with the second conductor with the semiconductor therebetween, and one of a source electrode and a drain electrode of the second transistor is electrically connected to the third conductor of the first transistor.

Claims (71)

1. A semiconductor device comprising:

a first transistor; and

a second transistor,

wherein the first transistor comprises:

a first conductor;

a second conductor;

a first insulator over the first conductor and the second conductor;

a semiconductor over the first insulator;

a second insulator over the semiconductor;

a third conductor over the second insulator; and

a fourth conductor and a fifth conductor that are in contact with the semiconductor,

wherein the third conductor includes a first region not overlapping the first conductor,

wherein the third conductor includes a second region overlapping the second conductor with the semiconductor therebetween, and

wherein one of a source and a drain of the second transistor is electrically connected to the third conductor.

2. The semiconductor device according to claim 1 , comprising a first memory cell and a second memory cell adjacent to each other,

wherein the first memory cell and the second memory cell each comprise:

the first transistor; and

the second transistor, and

wherein the first conductor included in the first memory cell is electrically connected to the first conductor included in the second memory cell.

3. The semiconductor device according to claim 1 , comprising a first memory cell and a second memory cell adjacent to each other,

wherein the first memory cell and the second memory cell each comprise:

the first transistor; and

the second transistor, and

wherein the second conductor included in the first memory cell is electrically connected to the second conductor included in the second memory cell.

4. The semiconductor device according to claim 1 , wherein the third conductor includes a region that does not overlap the second conductor.

5. The semiconductor device according to claim 1 ,

wherein the first conductor and the third conductor do not overlap with each other, and

wherein, when seen from the above, a distance between the first conductor and the third conductor is shorter than or equal to a distance between the first conductor and the second conductor.

6. The semiconductor device according to claim 1 ,

wherein the first conductor and the third conductor overlap with each other, and

wherein, when seen from the above, a width of a region where the first conductor and the third conductor overlap with each other is shorter than or equal to a distance between the first conductor and the second conductor.

7. The semiconductor device according to claim 1 ,

wherein the semiconductor is an oxide semiconductor, and

wherein a channel formation region of the second transistor includes an oxide semiconductor.

8. The semiconductor device according to claim 1 , wherein the second transistor is stacked over the first transistor.

9. The semiconductor device according to claim 1 , wherein any one state of 4 to 256 levels is held by the first transistor and the second transistor.

10. A radio-frequency tag comprising the semiconductor device according to claim 1 , further comprising an antenna.

11. An electronic device comprising the semiconductor device according to claim 1 , further comprising a printed wiring board.

12. A semiconductor device comprising:

a first transistor and a second transistor, the first transistor comprising:

a first conductor;

a second conductor;

a first insulator over the first conductor and the second conductor;

a semiconductor over the first insulator;

a second insulator over the semiconductor;

a third conductor over the second insulator; and

a fourth conductor and a fifth conductor that are in contact with the semiconductor,

wherein the semiconductor comprises a first region, a second region and a third region,

wherein the fourth conductor and the fifth conductor do not overlap the first region, second region and the third region,

wherein the first conductor overlaps the first region,

wherein the second conductor overlaps the second region,

wherein the third conductor overlaps the third region,

wherein the first region includes a region not overlapping the third region,

wherein the second region includes a region overlapping the third region, and

wherein one of a source and a drain of the second transistor is electrically connected to the third conductor of the first transistor.

13. The semiconductor device according to claim 12 , comprising a first memory cell and a second memory cell adjacent to each other,

wherein the first memory cell and the second memory cell each comprise the first transistor and the second transistor, and

wherein the first conductor included in the first memory cell is electrically connected to the first conductor included in the second memory cell.

14. The semiconductor device comprising according to claim 12 , comprising a first memory cell and a second memory cell adjacent to each other,

wherein the first memory cell and the second memory cell each comprise the first transistor and the second transistor, and

wherein the second conductor included in the first memory cell is electrically connected to the second conductor included in the second memory cell.

15. The semiconductor device according to claim 12 , wherein the second region is included in the third region.

16. The semiconductor device according to claim 12 ,

wherein the first region and the third region do not overlap with each other, and

wherein a distance between the first region and the third region is shorter than or equal to a distance between the first region and the second region.

17. The semiconductor device according to claim 12 ,

wherein the first region and the third region overlap with each other, and

wherein a width of a region where the first region and the third region overlap with each other is shorter than or equal to a distance between the first region and the second region.

18. The semiconductor device according to claim 12 , wherein an edge of the first region is aligned with an edge of the third region.

19. A radio-frequency tag comprising the semiconductor device according to claim 12 , further comprising an antenna.

20. An electronic device comprising the semiconductor device according to claim 12 , further comprising a printed wiring board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2015
From: KATO, KIYOSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 035258/0538 →
Priority Claims (1)
JP 2014-052211 · Mar 14, 2014 · national
Continuity (1)
Related Publication 20150263006A1 · Sep 17, 2015