IP Library Granted Patent US 9,299,940
Granted Patent B2
US 9,299,940 · App. 14/065,218 · Granted Mar 29, 2016

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

Inventors: Kuniharu Takei (Berkeley, CA); Toshitake Takahashi (Oakland, CA); Ali Javey (Emeryville, CA)
Assignee: The Regents of the University of California
H01L51/0558B82Y30/00H01L51/0048H01L51/0097H01L51/0545
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Quick Facts
Patent No.
US 9,299,940
App. No.
14/065,218
Granted
Mar 29, 2016
Kind
B2
Abstract

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Claims (31)

1. A device comprising:

a polymer substrate, the polymer substrate defining a mesh structure;

a gate electrode disposed on the polymer substrate;

a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate;

a carbon nanotube network disposed on the dielectric layer; and

a source electrode and a drain electrode disposed on the carbon nanotube network.

2. The device of claim 1 , further comprising:

a polymer layer disposed on the source electrode, the drain electrode, and exposed portions of the carbon nanotube network.

3. The device of claim 2 , wherein the polymer layer comprises poly(p-xylylene).

4. The device of claim 2 , wherein the polymer layer is about 250 nanometers to 1 micron thick.

5. The device of claim 1 , wherein an area defined by the device is about 2.5 microns to 7.5 microns by about 100 microns to 300 microns.

6. The device of claim 1 , wherein the gate electrode includes nickel, and wherein the source electrode and the drain electrode include palladium.

7. The device of claim 1 , wherein the carbon nanotube network is about 2 nanometers to 20 nanometers thick.

8. The device of claim 7 , wherein the carbon nanotube network has a density of about 10 to 100 nanotubes per micron area of the carbon nanotube network.

9. The device of claim 1 , wherein the device is mechanically flexible.

10. The device of claim 1 , wherein the dielectric layer is about 20 nanometers to 70 nanometers thick.

11. The device of claim 1 , wherein nanotubes of the carbon nanotube network have a length of about 0.4 microns to 0.12 microns.

12. The device of claim 1 , wherein nanotubes of the carbon nanotube network have a length of about 0.8 microns.

13. The device of claim 1 , wherein the dielectric layer comprises a first silicon oxide layer disposed on the gate electrode, an alumina layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the alumina layer.

14. The device of claim 1 , wherein the mesh structure includes a honeycomb mesh structure defining substantially hexagonal holes in the polymer substrate.

15. The device of claim 14 , wherein the device is located at an intersection of three lines of the honeycomb mesh structure.

16. The device of claim 14 , wherein each of the substantially hexagonal holes in the polymer substrate has sides having a length of about 0.5 millimeters to 2 millimeters.

17. The device of claim 1 , wherein a thickness of the polymer substrate is about 10 microns to 40 microns.

18. The device of claim 1 , wherein the polymer substrate comprises polyimide.

19. The device of claim 1 , wherein the source electrode and the drain electrode each include a layer of titanium disposed on the carbon nanotube network and a layer of palladium disposed on the layer of titanium.

20. A device comprising:

a polymer substrate, the polymer substrate defining a mesh structure;

a gate electrode disposed on the polymer substrate;

a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, the dielectric layer comprising a first silicon oxide layer disposed on the gate electrode, an alumina layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the alumina layer;

a carbon nanotube network disposed on the dielectric layer; and

a source electrode and a drain electrode disposed on the carbon nanotube network.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2014
From: TAKEI, KUNIHARU; TAKAHASHI, TOSHITAKE; JAVEY, ALI
To: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 032963/0486 →
CONFIRMATORY LICENSE Recorded Apr 24, 2014
From: REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE
To: ENERGY, UNITED STATES DEPARTMENT OF
Reel/Frame 032798/0748 →
Continuity (2)
Provisional Application 61721637 · Nov 2, 2012
Related Publication 20140124737A1 · May 8, 2014