IP Library Granted Patent US 9,300,891
Granted Patent B2
US 9,300,891 · App. 14/488,088 · Granted Mar 29, 2016

Solid-state imaging device and method of manufacturing the same

Inventors: Shunsuke Isono (Toyama, JP); Tetsuya Ueda (Toyama, JP); Tetsuo Satake (Toyama, JP); Takashi Hyakushima (Toyama, JP); Kenji Taki (Fukui, JP)
Assignee: Panasonic Intellectual Property Management Co., Ltd.
H04N5/372H01L27/14683H01L27/307
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Quick Facts
Patent No.
US 9,300,891
App. No.
14/488,088
Granted
Mar 29, 2016
Kind
B2
Abstract

A solid-state imaging device according to the present disclosure includes: a pixel region which includes: pixel plugs formed above and electrically connected to a charge accumulation and diffusion layer, the pixel plugs respectively corresponding to pixels; lower pixel electrodes formed on and electrically connected to the pixel plugs, respectively, the lower pixel electrodes respectively corresponding to the pixels; an organic photoelectric conversion film formed on and electrically connected to the lower pixel electrodes; and an upper pixel electrode formed on and electrically connected to the organic photoelectric conversion film, and in which top surfaces of a global interconnect, a light shielding film, and a first AI pad formed in an uppermost layer of a multilayer interconnect structure disposed in a peripheral region is above a bottom surface of the organic photoelectric conversion film, the peripheral region being peripheral to the pixel region.

Claims (44)

1. A solid-state imaging device comprising:

a pixel region in which a plurality of pixels are disposed in a matrix above a semiconductor substrate; and

a peripheral region in which a multilayer interconnect structure for driving the plurality of pixels is formed, the peripheral region being peripheral to the pixel region in a plan view of the semiconductor substrate,

wherein the pixel region includes:

a charge accumulation and diffusion layer in the semiconductor substrate;

a plurality of pixel plugs formed above and electrically connected to the charge accumulation and diffusion layer, the plurality of pixel plugs respectively corresponding to the plurality of pixels;

a plurality of lower pixel electrodes formed on and electrically connected to the plurality of pixel plugs, respectively, the plurality of lower pixel electrodes respectively corresponding to the plurality of pixels;

a photoelectric conversion film formed on and electrically connected to the plurality of lower pixel electrodes; and

an upper pixel electrode formed on and electrically connected to the photoelectric conversion film, and

a top surface of an interconnect formed in an uppermost layer of the multilayer interconnect structure disposed in the peripheral region is above a bottom surface of the photoelectric conversion film.

2. The solid-state imaging device according to claim 1 ,

wherein the interconnect formed in the uppermost layer includes power supply line for supplying a power supply voltage to a circuit and a pad for wire bonding.

3. The solid-state imaging device according to claim 2 ,

wherein the power supply line, the pad, and a light shielding film for partially shielding the plurality of pixels have a same film thickness.

4. The solid-state imaging device according to claim 2 ,

wherein the power supply line, the pad, and a light shielding film for partially shielding the plurality of pixels include a same material.

5. The solid-state imaging device according to claim 4 ,

wherein the material included in the power supply line, the pad, and the light shielding film contains Al.

6. The solid-state imaging device according to claim 3 ,

wherein bottom surfaces of the power supply line and the pad are below a bottom surface of the light shielding film.

7. The solid-state imaging device according to claim 1 ,

wherein the multilayer interconnect structure contains Cu.

8. The solid-state imaging device according to claim 1 ,

wherein the plurality of lower pixel electrodes contain Ti or a chemical compound of Ti.

9. The solid-state imaging device according to claim 1 ,

wherein the plurality of pixel plugs contain Cu.

10. The solid-state imaging device according to claim 1 ,

wherein ring-shaped pattern is also disposed above an end portion of the upper pixel electrode to surround the pixel region in the plan view of the semiconductor substrate.

11. The solid-state imaging device according to claim 1 , further comprising

a protective film on the upper pixel electrode, for protecting the upper pixel electrode and the photoelectric conversion film,

wherein an end face of the upper pixel electrode is on a same plane with an end face of the protective film, and

the end face of the upper pixel electrode and the end face of the protective film form an angle of 45 degrees or more with a surface of the semiconductor substrate.

12. The solid-state imaging device according to claim 1 ,

wherein at an end portion of the photoelectric conversion film, the photoelectric conversion film continuously becomes thinner toward a periphery.

13. The solid-state imaging device according to claim 1 ,

wherein in the plan view of the semiconductor substrate, the upper pixel electrode is formed to cover the plurality of lower pixel electrodes.

14. A method of manufacturing a solid-state imaging device, the method comprising:

forming a charge accumulation and diffusion layer in a semiconductor substrate in a pixel region in which a plurality of pixels are disposed in a matrix above the semiconductor substrate;

forming a pixel plug to be positioned above and electrically connected to the charge accumulation and diffusion layer;

forming, in the following sequence, a lower pixel electrode, a photoelectric conversion film, and an upper pixel electrode in a stack, to be positioned above and electrically connected to the pixel plug; and

after forming the photoelectric conversion film, forming an interconnect in an uppermost layer of a multilayer interconnect structure so that a top surface of the interconnect is above a bottom surface of the photoelectric conversion film, the multilayer interconnect structure being disposed in a peripheral region peripheral to the pixel region in a plan view of the semiconductor substrate.

15. The method of manufacturing a solid-state imaging device according to claim 14 ,

wherein in the forming of the photoelectric conversion film, the photoelectric conversion film is formed by a shadow mask method, and

in each process subsequent to the forming of the photoelectric conversion film, dry etching and ashing are performed at a substrate temperature of 200° C. or below and a plasma emission wavelength of 350 nm or greater.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2014
From: ISONO, SHUNSUKE; UEDA, TETSUYA; SATAKE, TETSUO; HYAKUSHIMA, TAKASHI; TAKI, KENJI
To: PANASONIC CORPORATION
Reel/Frame 033896/0985 →
Priority Claims (1)
JP 2012-287603 · Dec 28, 2012 · national
Continuity (2)
Continuation PCTJP2013006847 · Nov 21, 2013
Related Publication 20150002719A1 · Jan 1, 2015