Dynamic voltage and frequency management based on active processors
In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
1. An apparatus comprising:
a plurality of processors;
a power control circuit coupled to the plurality of processors, wherein the power control unit is programmable with data describing a plurality of operating points for the plurality of processors, and wherein the data further includes an indication for each respective operating point of the plurality of operating points indicating a limit to a first number of active processors in the plurality of processors at the respective operating point, wherein exceeding the limit of active processors at the respective operating point would exceed a capability of a power management unit that provides power to the plurality of processors when the active processors are consuming a maximum amount of power, and wherein the power control circuit is configured to detect that a second number of processors to be active exceeds the limit for a selected operating point and to override the selected operating point with a second operating point responsive to the detecting.
2. The apparatus as recited in claim 1 wherein the second operating point is a lower-power operating point than the selected operating point.
3. The apparatus as recited in claim 2 wherein a clock frequency for the plurality of processors in the second operating point is lower than a clock frequency for the plurality of processors in the selected operating point.
4. The apparatus as recited in claim 2 wherein a supply voltage magnitude for the plurality of processors in the second operating point is lower than a supply voltage magnitude for the plurality of processors in the selected operating point.
5. The apparatus as recited in claim 1 wherein the power control circuit is configured to detect that the second number of processors to be active exceeds the limit responsive to a request to activate a first processor of the plurality of processors, and wherein the selected operating point is a current operating point at a time that the request to activate the first processor is received.
6. The apparatus as recited in claim 1 wherein the power control circuit is configured to detect that the second number of processors to be active exceeds the limit responsive to a request to change a current operating point of the plurality of processors to the selected operating point.
7. The apparatus as recited in claim 1 wherein the power control circuit is configured to detect that the first number of active processors is less than the limit responsive to one of the plurality of processors deactivating while a current operating point of the plurality of processors is the second operating point, and wherein the power control circuit is configured to change to the selected operating point responsive to detecting the deactivation.
8. The apparatus as recited in claim 1 wherein the plurality of processors and the power control circuit are integrated into an integrated circuit, and wherein the integrated circuit further comprises a power manager circuit configured to communicate power supply voltage magnitude requests for the integrated circuit external to the integrated circuit, and wherein the power manager circuit is coupled to receive a requested supply voltage magnitude from the power control circuit for the plurality of processors, wherein the requested supply voltage magnitude is specified by the selected operating point or the second operating point dependent on whether or not the second operating point is overriding the selected operating point.
9. The apparatus as recited in claim 1 wherein the indication comprises a bit vector for each number of processors in excess of a number that are permitted at a highest one of the plurality of operating points, wherein if a corresponding bit is set, the corresponding number exceeds the limit at the respective operating point.
10. The apparatus as recited in claim 9 wherein the power control circuit supports a plurality of overriding operating points including the second operating point, where each of the plurality of overriding operating points corresponds to a different number of active processors represented in the bit vector.
11. The apparatus as recited in claim 1 further comprising a digital power estimator coupled to the plurality of processors and configured to estimate an amount of power consumed by the plurality of processors, and wherein the digital power estimator is configured to throttle one or more of the plurality of processors responsive to the amount of power exceeding a threshold amount.
12. A method comprising:
monitoring a first number of active processors of a plurality of processors in a system;
detecting that a second number of processors to be active exceeds a maximum number of active processors that is permissible for a present supply voltage magnitude and a present clock frequency supplied to the plurality of processors, wherein the detecting is responsive to a request to activate one of the plurality of processors that is currently inactive, and wherein exceeding the maximum number of active processors at the present operating point would exceed a capability of a power management unit that provides power to the plurality of processors when the active processors are consuming a maximum amount of power; and
reducing the present supply voltage magnitude and the present clock frequency to a lower supply voltage magnitude and a lower clock frequency responsive to detecting that the number exceeds the maximum number.
13. The method as recited in claim 12 further comprising:
detecting that a third number of currently active processors exceeds the maximum number of active processors that are permissible for a requested supply voltage magnitude and a requested clock frequency to be supplied to the plurality of processors; and
changing the present supply voltage magnitude to a second supply voltage magnitude that is less than the requested supply voltage magnitude responsive to the detecting and changing the present clock frequency to a second clock frequency that is less than the requested clock frequency responsive to the detecting.
14. The method as recited in claim 13 further comprising:
detecting a deactivation of one of the active processors, wherein the deactivation reduces the number of active processors to a fourth number that is permissible for the requested supply voltage magnitude and the requested clock frequency; and
changing the present supply voltage magnitude to the requested supply voltage magnitude responsive to the detecting and changing the present clock frequency to the requested clock frequency responsive to the detecting.
15. The method as recited in claim 12 further comprising:
detecting a deactivation of one of the active processors, wherein the deactivation reduces the number of active processors to a fifth number that is permissible for the present supply voltage magnitude and the present clock frequency; and
restoring the present supply voltage magnitude and the present clock frequency responsive to the detecting.
16. The method as recited in claim 12 further comprising:
during a time that the present clock frequency is reducing to the lower clock frequency and the present supply voltage magnitude is reducing to the lower supply voltage magnitude, dividing the clock frequency by N, where N is an integer greater than one.
17. The method as recited in claim 16 further comprising stopping the dividing subsequent to completing the reducing.
18. A system comprising:
a power management unit configured to supply a plurality of supply voltages to a system on a chip; and
the system on a chip coupled to the power management unit, wherein the system on a chip comprises:
a power manager circuit configured to request a plurality of supply voltage magnitudes for the plurality of supply voltages from the power management unit; and
a central processing unit complex comprising a plurality of processors and a power control circuit coupled to the plurality of processors, wherein the power control circuit is configured to automatically reduce an operating point of the plurality of processors responsive to a number of active processors of the plurality of processors that are to be active exceeding a maximum number of active processors associated with the operating point, and wherein the power control circuit is configured to transmit a requested supply voltage magnitude to the power manager circuit responsive to the reducing, and wherein exceeding the maximum number of active processors at the operating point would exceed a capability of the power management unit when the active processors are consuming a maximum amount of power.
19. The system as recited in claim 18 further comprising the power control circuit restoring the operating point responsive to detecting that the number of processors to be active is less than or equal to the maximum number associated with the operating point.
20. The system as recited in claim 18 wherein the power control circuit is programmable with data representing a plurality of operating points and a plurality of indications of the maximum number, each of the plurality of indications associated with a respective one of the plurality of operating points.