Memory system and bank interleaving method
According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.
1. A memory system comprising:
a memory controller;
a first memory chip having a first I/O terminal;
a second memory chip having a second I/O terminal; and
a signal line connecting the first I/O terminal and the second I/O terminal commonly to the memory controller, the signal line being used to transmit data between the first memory chip and the memory controller and between the second memory chip and the memory controller, and to transmit a command from the memory controller to the first memory chip and the second memory chip;
wherein the memory controller outputs a first read command to the first memory chip and then outputs a second read command to the second memory chip, outputs a first data transfer command to the first memory chip after receiving read completion notification associated with the first read command from the first memory chip, outputs a third read command to the first memory chip after receiving all data associated with the first read command from the first memory chip in response to the first data transfer command, and then outputs a second data transfer command to the second memory chip to receive data associated with the second read command from the second memory chip.
2. The memory system according to claim 1 , wherein the memory controller receives data associated with the second read command from the second memory chip in response to the second data transfer command while the first memory chip is internally reading data associated with the third read command from a memory cell array on the first memory chip.
3. The memory system according to claim 2 , wherein the memory controller outputs a fourth read command to the second memory chip after receiving all data associated with the second read command from the memory chip in response to the second data transfer command while the first memory chip is internally reading data associated with the third read command from the memory cell array on the first memory chip.
4. The memory system according to claim 1 , wherein the first memory chip further has a status signal terminal and the memory system further comprises a status signal line connecting the status signal terminal and the memory controller, and the first memory chip uses the status signal line to provide the read completion notification from the first memory chip to the memory controller.