IP Library Granted Patent US 9,304,750
Granted Patent B2
US 9,304,750 · App. 12/685,477 · Granted Apr 5, 2016

System and method for processor with predictive memory retrieval assist

Inventor: Dean A. Klein (Eagle, ID)
Assignee: Micron Technology, Inc.
G06F8/445G06F12/0215
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Quick Facts
Patent No.
US 9,304,750
App. No.
12/685,477
Granted
Apr 5, 2016
Kind
B2
Abstract

A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.

Claims (48)

1. A method for managing memory, the method comprising:

accessing a reference table contained in object code;

determining whether an instruction in an execution pipeline references information in the reference table, wherein the reference table includes an indication of a memory location corresponding to the information;

if the instruction references the information, initiating opening of the memory location corresponding to the information before executing the instruction.

2. The method of claim 1 , wherein accessing the reference table comprises receiving the reference table.

3. The method of claim 1 , wherein determining whether an instruction in the execution pipeline references information in the reference table comprises parsing the execution pipeline.

4. The method of claim 1 , wherein the indication comprises an address in memory.

5. The method of claim 4 , wherein initiating opening of the memory location comprises signaling a memory controller to retrieve information stored at the address.

6. The method of claim 4 , wherein determining whether an instruction in an execution pipeline references information in the reference table comprises determining whether an instruction in an execution pipeline invokes a branch, routine call, and/or a data reference.

7. The method of claim 4 , wherein the address comprises an offset address.

8. The method of claim 1 , further comprising generating the reference table.

9. The method of claim 8 , wherein generating the reference table comprises generating the reference table using a compiler.

10. The method of claim 9 , wherein generating the reference table comprises generating the reference table using an assembler.

11. The method of claim 1 , further comprising storing the reference table.

12. The method of claim 11 , wherein storing the reference table comprises storing the reference table in a reference table buffer.

13. The method of claim 1 , further comprising accessing a routine, wherein the reference table is accessed if the routine includes the reference table.

14. The method of claim 13 , wherein accessing a routine comprises accessing a program.

15. The method of claim 1 , wherein if the instruction references information in the reference table, looking up the indication of the memory location corresponding to the referenced information.

16. The method of claim 1 , wherein initiating opening of the memory location comprises transmitting an address to a memory controller.

17. The method of claim 1 , wherein determining whether an instruction in an execution pipeline references information in the reference table comprises determining whether an instruction queued in the execution pipeline invokes a reference in the reference table.

18. The method of claim 1 , wherein the reference table precedes the instruction in the object code.

19. The method of claim 1 , further comprising determining whether the reference table is a suitable reference table before accessing the reference table.

20. The method of claim 19 , wherein determining whether the reference table is a suitable reference table comprises determining whether the reference table includes a signature.

21. The method of claim 1 , wherein the instruction comprises a conditional branch instruction.

22. The method of claim 1 , further comprising providing the table to the memory management processor.

23. The method of claim 1 , further comprising loading instructions into the execution pipeline.

24. The method of claim 1 , wherein accessing a reference table contained in object code comprises a memory management processor accessing the reference table.

25. The method of claim 1 , wherein determining whether an instruction in an execution pipeline references information in the reference table comprises a memory management processor determining whether an instruction in an execution pipeline references information in the reference table.

26. The method of claim 1 , wherein initiating opening of the memory location prior to executing the instruction comprises a memory management processor initiating opening of the memory location prior to executing the instruction.

27. The method of claim 1 , wherein determining whether an instruction in the execution pipeline references information in the reference table comprises parsing instructions in the execution pipeline.

28. A method for managing memory, the method comprising:

accessing a reference table contained in object code;

determining whether an instruction in an execution pipeline references information in the reference table, wherein the reference table includes an indication of a memory location corresponding to the information;

if the instruction references the information, initiating opening of the memory location corresponding to the information before executing the instruction; and

retrieving the referenced information.

29. The method of claim 28 , wherein retrieving the reference information comprises retrieving the referenced information from system memory.

30. The method of claim 28 , wherein retrieving the referenced information comprises retrieving the referenced information from cache memory.

31. The method of claim 28 , further comprising inserting the retrieved information into the execution pipeline.

32. The method of claim 31 , wherein the referenced information comprises a variable, retrieving the referenced information comprises retrieving a value for a variable and inserting the retrieved referenced information comprises inserting the value of the variable in the instruction.

33. The method of claim 31 , wherein retrieving the referenced information comprises retrieving instructions from a routine and wherein inserting the retrieved referenced information comprises inserting the retrieved instructions following the instruction that referenced the information.

34. A method for managing memory, the method comprising:

accessing a reference table contained in object code;

routing the reference table to a memory management processor;

determining whether an instruction in an execution pipeline references information in the reference table, wherein the reference table includes an indication of a memory location corresponding to the information; and

if the instruction references the information, initiating opening of the memory location corresponding to the information before executing the instruction.

35. The method of claim 34 , further comprising signifying to a memory controller that the reference table should be routed to the memory management processor.

36. The method of claim 34 , further comprising routing the reference table to the memory management processor as the object code is received by a processing unit that includes the memory management processor.

37. The method of claim 34 , wherein routing the reference table to the memory management processor comprises a memory controller routing the reference table to the memory management processor.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (4)
Continuation 12361400 · Jan 28, 2009
Continuation 11240099 · Sep 30, 2005
Continuation 10192957 · Jul 11, 2002
Related Publication 20100115221A1 · May 6, 2010