Single photomask high precision thin film resistor

1. A method of forming an integrated circuit, comprising the steps of:

forming a lower dielectric layer above active components of said integrated circuit;

forming electrodes in said lower dielectric layer, such that top surfaces of said electrodes are substantially coplanar with a top surface of said lower dielectric layer between said electrodes;

forming a layer of resistor material over said lower dielectric layer and over said electrodes;

forming a resistor mask over said layer of resistor material which overlaps said electrodes;

removing said layer of resistor material in areas exposed by said resistor mask to form a thin film resistor, said thin film resistor making electrical connections to said top surfaces of said electrodes at a bottom surface of said thin film resistor; and

forming an upper dielectric layer over said thin film resistor and said lower dielectric layer, so that a top surface of said thin film resistor is free of electrical connections.

2. The method of claim 1 , in which said layer of resistor material comprises a resistive material selected from the group consisting of nickel chromium, silicon chromium and tantalum silicon nitride.

3. The method of claim 1 , in which said step of forming said electrodes in said lower dielectric layer comprises steps:

forming interconnect trenches in said lower dielectric layer;

forming a metal liner over said lower dielectric layer and extending into said interconnect trenches;

forming layer of fill metal comprising copper on said metal liner, said layer of fill metal filling said interconnect trenches; and

removing said fill metal and said metal liner from over said lower dielectric layer, leaving said electrodes in said lower dielectric layer.

4. The method of claim 1 , in which said step of forming said electrodes in said lower dielectric layer comprises steps:

forming via holes in said lower dielectric layer, said via holed exposing electrical connections;

forming a metal liner over said lower dielectric layer and extending into said via holes;

forming layer of fill metal on said metal liner, said layer of fill metal filling said via holes; and

removing said fill metal and said metal liner from over said lower dielectric layer, leaving said electrodes in said lower dielectric layer, said electrodes making contact to said electrical connections.

5. The method of claim 4 , in which said layer of fill metal comprises tungsten.

6. The method of claim 4 , in which said layer of fill metal comprises copper.

7. A method of forming an integrated circuit, comprising the steps of:

forming a base dielectric layer above active components of said integrated circuit;

forming electrodes over said base dielectric layer;

forming a lower dielectric layer over said base dielectric layer, said lower dielectric layer abutting and surrounding said electrodes, so that top surfaces of said electrodes are substantially coplanar with a top surface of said lower dielectric layer between said electrodes;

forming a layer of resistor material over said lower dielectric layer and over said electrodes;

forming a resistor mask over said layer of resistor material which overlaps said electrodes;

removing said layer of resistor material in areas exposed by said resistor mask to form a thin film resistor, said thin film resistor making electrical connections to said top surfaces of said electrodes at a bottom surface of said thin film resistor; and

forming an upper dielectric layer over said thin film resistor and said lower dielectric layer, so that a top surface of said thin film resistor is free of electrical connections.

8. The method of claim 7 , in which said layer of resistor material comprises a resistive material selected from the group consisting of nickel chromium, silicon chromium and tantalum silicon nitride.

9. The method of claim 7 , in which said step of forming said electrodes comprises steps:

forming a layer of interconnect metal over said base dielectric layer, said layer of interconnect metal comprising a layer of aluminum-based metal;

forming an electrode mask over said layer of interconnect metal;

removing said layer of interconnect metal in areas exposed by said electrode mask to form said electrodes; and

removing said electrode mask.

10. A method of forming an integrated circuit, comprising the steps of:

forming a lower dielectric layer with electrodes embedded therein using a planarization process that exposes both the lower dielectric layer and the electrodes at a substantially coplanar surface;

forming a layer of resistor material over and touching said lower dielectric layer and over said electrodes;

forming a resistor mask over said layer of resistor material which overlaps said electrodes;

removing said layer of resistor material in areas exposed by said resistor mask to form a thin film resistor, said thin film resistor making electrical connections to said top surfaces of said electrodes at a bottom surface of said thin film resistor; and

forming an upper dielectric layer over said thin film resistor and said lower dielectric layer, so that a top surface of said thin film resistor is free of electrical connections.

11. The method of claim 10 , further comprising forming head contacts between the electrodes and the thin film resistor.