DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.
1. A power supply system comprising:
a Quad Flat No-Lead (QFN)-type leadframe having a plurality of leads and a pad with a first and a second pad surface, the first pad surface having a recessed portion and an un-recessed portion, the recessed portion having a depth and an outline suitable for attaching a plurality of semiconductor chips, the pad tie-able to a switch node terminal of the system;
a driver-and-controller chip attached to the second pad surface, said driver-and-controller chip having a plurality of terminals tied by bonding wires to respective leads of the lead frame, which will then pre-molded as a carrier with a exposed recessed surface;
a package encapsulating the driver-and-controller chip, the wires and the second surface of the pad and leads, but leaving the first pad surface and at least some of the plurality of leads un-encapsulated creating a pre-molded carrier;
a first Field Effect Transistor (FET) chip having a drain terminal of the first FET chip attached to the recessed portion of the first pad surface, and further having a source terminal of the first FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface, the source terminal of the first FET chip tie-able to a board terminal as a grounded output terminal of the system; and
a second FET chip having a source terminal of the second FET chip attached to the recessed portion of the first pad surface, and further having a drain terminal of the second FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface, the drain of the second FET chip tie-able to a board terminal as an input terminal of the system.
2. The system of claim 1 wherein the first FET chip includes a drain FET, which serves as a low-side transistor attached to the recessed portion of the pre-molded carrier.
3. The system of claim 2 wherein the second FET chip includes a source down FET, which serves as a high-side transistor attached to the recessed portion of the pre-molded carrier.
4. A multichip semiconductor package comprising:
a Quad Flat No-Lead (QFN)-type leadframe having a plurality of leads and a pad with a first and a second pad surface, the first pad surface having a recessed portion and an un-recessed portion, the recessed portion having a depth and an outline suitable for attaching a plurality of semiconductor chips, the pad tie-able to a switch node terminal of the system;
a driver-and-controller chip attached to the second pad surface, said driver-and-controller chip having a plurality of terminals tied by bonding wires to respective leads of the lead frame, which will then pre-molded as a carrier with a exposed recessed surface;
a package encapsulating the driver-and-controller chip, the wires and the second surface of the pad and leads, but leaving the first pad surface and at least some of the plurality of leads un-encapsulated creating a pre-molded carrier;
a first Field Effect Transistor (FET) chip having a drain terminal of the first FET chip attached to the recessed portion of the first pad surface, and further having a source terminal of the first FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface, the source terminal of the first FET chip tie-able to a board terminal as a grounded output terminal of the system; and
a second FET chip having a source terminal of the second FET chip attached to the recessed portion of the first pad surface, and further having a drain terminal of the second FET chip and the gate terminal co-planar with the un-recessed portion of the first pad surface, the drain of the second FET chip tie-able to a board terminal as an input terminal of the system.
5. The multichip semiconductor package of claim 4 wherein the first FET chip includes a drain FET, which serves as a low-side transistor.
6. The multichip semiconductor package of claim 5 wherein the second FET chip includes a source down FET, which serves as a high-side transistor.
7. The system of claim 2 , wherein in the two attached transistors form a converter with the terminals tied through the recessed portion of the pre-molded carrier.
8. The system of claim 3 , wherein in the two attached transistors form a converter with the terminals tied through the recessed portion of the pre-molded carrier.