IP Library Granted Patent US 9,305,943
Granted Patent B2
US 9,305,943 · App. 14/368,983 · Granted Apr 5, 2016

Array substrate and repairing method thereof and display device

Inventors: Xiangyang Xu (Beijing, CN); Hui Wang (Beijing, CN)
Assignees: BOE TECHNOLOGY GROUP CO., LTD.; HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
H01L27/124G02F1/13452G02F1/136259G09G3/36H01L22/22G02F2001/136263G02F2001/136272G09G2300/0426G09G2330/08
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Quick Facts
Patent No.
US 9,305,943
App. No.
14/368,983
Granted
Apr 5, 2016
Kind
B2
Abstract

An array substrate, a repairing method thereof and a display device, wherein the array substrate includes: a plurality of gate lines and a plurality of data lines provided in a display region, gate lead lines provided in a non-display region and respectively connected to the gate lines and a gate driver IC, and data lead lines provided in the non-display region and respectively connected to the data lines and a data driver IC. The array substrate further includes: at least one first repairing line provided in a same layer as the gate lead lines, and at a position corresponding to a data lead line; and/or, at least one second repairing line provided in a same layer as the data lead lines, and at a position corresponding to a gate lead line.

Claims (33)

1. An array substrate, comprising:

a plurality of gate lines and a plurality of data lines, disposed in a display region;

gate lead lines, disposed in a non-display region and respectively connected to the gate lines and a gate driver integrated circuit;

data lead lines, disposed in the non-display region and respectively connected to the data lines and a data driver integrated circuit;

at least one first repairing line, disposed in a same layer as the gate lead lines, and at a position corresponding to a data lead line; and/or

at least one second repairing line, disposed in a same layer as the data lead lines, and at a position corresponding to a gate lead line.

2. The array substrate as claimed in claim 1 , wherein each first repairing line corresponds to one different data lead line.

3. The array substrate as claimed in claim 2 , wherein two ends of each first repairing line are disposed in a dangling state.

4. The array substrate as claimed in claim 2 , wherein each second repairing line corresponds to one different gate lead line.

5. The array substrate as claimed in claim 2 , wherein two ends of each second repairing line are disposed in a dangling state.

6. The array substrate as claimed in claim 2 , wherein if the gate driver integrated circuit is disposed on the array substrate, the array substrate further comprises:

at least one peripheral layout gate, respectively connected to the gate driver integrated circuit and an external printed circuit board; and

at least one third repairing line, disposed in a same layer as the data lead lines, and at a position corresponding to the peripheral layout gate.

7. The array substrate as claimed in claim 6 , wherein each third repairing line corresponds to one different peripheral layout gate.

8. The array substrate as claimed in claim 6 , wherein two ends of each third repairing line are disposed in a dangling state.

9. The array substrate as claimed in claim 1 , wherein two ends of each first repairing line are disposed in a dangling state.

10. The array substrate as claimed in claim 1 , wherein each second repairing line corresponds to one different gate lead line.

11. The array substrate as claimed in claim 10 , wherein if the gate driver integrated circuit is disposed on the array substrate, the array substrate further comprises:

at least one peripheral layout gate, respectively connected to the gate driver integrated circuit and an external printed circuit board; and

at least one third repairing line, disposed in a same layer as the data lead lines, and at a position corresponding to the peripheral layout gate.

12. The array substrate as claimed in claim 1 , wherein two ends of each second repairing line are disposed in a dangling state.

13. The array substrate as claimed in claim 1 , wherein if the gate driver integrated circuit is disposed on the array substrate, the array substrate further comprises:

at least one peripheral layout gate, respectively connected to the gate driver integrated circuit and an external printed circuit board; and

at least one third repairing line, disposed in a same layer as the data lead lines, and at a position corresponding to the peripheral layout gate.

14. The array substrate as claimed in claim 13 , wherein each third repairing line corresponds to one different peripheral layout gate.

15. The array substrate as claimed in claim 14 , wherein two ends of each third repairing line are disposed in a dangling state.

16. The array substrate as claimed in claim 13 , wherein two ends of each third repairing line are disposed in a dangling state.

17. A display device, comprising the array substrate as claimed in claim 1 .

18. A repairing method of an array substrate, comprising:

when a certain data lead line of an array substrate is detected to be disconnected, respectively performing a laser dot fusion process at positions on the array substrate corresponding to two ends of a position of a data lead line where a disconnection occurs, so that a first repairing line corresponding to the data lead line and the data lead line are fused together, wherein the first repairing line and a gate lead line of the array substrate are disposed in a same layer and at a position corresponding to the data lead line; or

when a certain gate lead line of the array substrate is detected to be disconnected, respectively performing a laser dot fusion process at positions on the array substrate corresponding to two ends of a position of the gate lead line where a disconnection occurs, so that a second repairing line corresponding to the gate lead line and the gate lead line are fused together, wherein the second repairing line and the data lead line are disposed in a same layer and at a position corresponding to the gate lead line.

19. The method as claimed in claim 18 , further comprising:

when a certain peripheral layout gate of the array substrate is detected to be disconnected, respectively performing a laser dot fusion process at positions on the array substrate corresponding to two ends of a position of the peripheral layout gate where a disconnection occurs, so that a third repairing line corresponding to the peripheral layout gate and the peripheral layout gate are fused together, wherein the third repairing line and the data lead line are disposed in a same layer and at a position corresponding to the peripheral layout gate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2014
From: XU, XIANGYANG; WANG, HUI
To: BOE TECHNOLOGY GROUP CO., LTD.; HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 033187/0944 →
Priority Claims (1)
CN 2013 1 0216603 · Jun 3, 2013 · national
Continuity (1)
Related Publication 20150108480A1 · Apr 23, 2015