IP Library Granted Patent US 9,306,013
Granted Patent B2
US 9,306,013 · App. 14/286,805 · Granted Apr 5, 2016

Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies

Inventors: Jeffrey A. Babcock (Sunnyvale, CA); Alexei Sadovnikov (Sunnyvale, CA)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L29/402H01L29/66553H01L29/66681H01L29/7824
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Quick Facts
Patent No.
US 9,306,013
App. No.
14/286,805
Granted
Apr 5, 2016
Kind
B2
Abstract

A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Claims (7)

1. A method, comprising:

developing a bipolar transistor region on a substrate;

developing a laterally diffused metal oxide semiconductor (LDMOS) transistor region on the substrate and spaced apart from the bipolar transistor;

depositing an epitaxial polysilicon layer over the bipolar transistor region and the LDMOS transistor region; and

patterning and etching the epitaxial polysilicon layer using a single mask to form:

a base above the bipolar transistor region; and

a gate shield above the LDMOS transistor region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2015
From: BABCOCK, JEFFREY A.; SADOVNIKOV, ALEXEI
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 034613/0768 →
Continuity (1)
Related Publication 20150340448A1 · Nov 26, 2015