Stable amorphous metal oxide semiconductor
A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.
1. A thin film semiconductor device comprising:
a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide with an energy gap less than approximately 4 ev and an amorphous insulating covalent metal oxide with an energy gap greater than approximately 6 ev;
a pair of terminals positioned in communication with the semiconductor layer and defining a conductive channel; and
a gate terminal in communication with the conductive channel and positioned to control conduction of the channel.
2. A thin film semiconductor device as claimed in claim 1 wherein the amorphous semiconductor ionic metal oxide is in an amount greater than the amorphous insulating covalent metal oxide.
3. A thin film semiconductor device as claimed in claim 1 wherein the amount of amorphous semiconductor ionic metal oxide is greater than approximately 17% of the mixture.
4. A thin film semiconductor device as claimed in claim 1 wherein the amount of amorphous insulating covalent metal oxide is greater than approximately 5% of the mixture, the amount preventing the amorphous semiconductor ionic metal oxide from becoming poly crystalline at processing temperatures and allowing a continuous network of the amorphous semiconductor ionic metal oxide.
5. A thin film semiconductor device as claimed in claim 4 wherein the amount of amorphous insulating covalent metal oxide is sufficient to prevent the amorphous semiconductor ionic metal oxide from becoming poly crystalline at processing temperatures in a range of approximately 250° C. to approximately 700° C.
6. A thin film semiconductor device as claimed in claim 1 wherein the amorphous semiconductor ionic metal oxide includes one of zinc oxide, indium oxide, tin oxide, gallium oxide, cadmium oxide, or combinations thereof.
7. A thin film semiconductor device as claimed in claim 1 wherein the amorphous insulating covalent metal oxide includes one of aluminum oxide, silicon oxide, magnesium oxide, beryllium oxide, boron oxide, or combinations thereof.
8. A thin film semiconductor device as claimed in claim 1 wherein the mixture is represented by one of the formula XO a YO b , and X-O-Y, where YO is an amorphous insulating covalent metal oxide and XO is an amorphous semiconductor ionic metal oxide and where ‘a’ is the amount of amorphous semiconductor ionic metal oxide in the composite mixture and ‘b’ is the amount of amorphous insulating covalent metal oxide in the composite mixture and where ‘a’ and ‘b’ are >0.
9. A thin film semiconductor device comprising:
a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide with an energy gap less than approximately 4 ev and an amorphous insulating covalent metal oxide with an energy gap greater than approximately 6 ev, wherein the amounts of amorphous semiconductor ionic metal oxide and the amorphous insulating covalent metal oxide are greater than 0% of the mixture and the amorphous insulating covalent metal oxide is greater than approximately 5% of the mixture, and wherein the amount of amorphous insulating covalent metal oxide is sufficiently large to prevent the amorphous semiconductor ionic metal oxide from becoming poly crystalline at processing temperatures and is sufficiently small to allow a continuous network of the amorphous semiconductor ionic metal oxide;
a pair of terminals positioned in communication with the semiconductor layer and defining a conductive channel; and
a gate terminal in communication with the conductive channel and positioned to control conduction of the channel.