Duty cycle adjustment with error resiliency

1. A method for adjusting a duty cycle, comprising:

generating a duty cycle signal having a voltage representing a duty cycle of a clock signal;

generating, using a reference voltage generator, in response to a reference control signal, a reference voltage from voltage sources applied to the reference voltage generator; and

comparing, using the comparator, the reference voltage and the duty cycle signal;

adjusting, using a clock evaluation control circuit, the reference voltage generated by the adjustable reference voltage generator to match the duty cycle signal to produce a first matched value;

inverting supply voltage sources input to the reference voltage generator in response to an applied reference polarity signal;

adjusting, using the clock evaluation control circuit, while the supply voltage sources are inverted, the reference voltage to match the duty cycle signal to produce a second matched value; and

swapping comparator inputs into the comparator in response to an applied comparator polarity signal; and

while the comparator inputs are swapped:

adjusting, using the clock evaluation control circuit, the reference voltage generated by the adjustable reference voltage generator to match the duty cycle signal to produce a third matched value;

inverting the supply voltage sources of the reference voltage generator;

adjusting, using the clock evaluation control circuit, while the supply voltage sources are inverted, the reference voltage to produce a fourth matched value; and

calculating a duty cycle value based on the first, second, third, and fourth matched values.

2. The method of claim 1 , wherein generating a duty cycle signal further comprises:

sampling the clock signal from a clock distribution circuit; and

generating the duty cycle signal as an analog signal.

3. The method of claim 1 , wherein adjusting the reference voltage generated by the adjustable reference voltage generator involves using a binary search to determine the first and second matched values.

4. The method of claim 3 , further comprising:

applying the comparator polarity signal and the reference polarity signal to produce multiple clock signal phases representing different circuit configurations,

producing a phase clock measurement for each circuit configuration;

averaging the phase clock measurements to approximate a clock voltage measurement value; and

performing the binary search to match the reference voltage to the clock voltage measurement value.

5. The method of claim 4 , further comprising:

performing said binary search by evaluating one of:

V ref >V CLK : X i =X i-1− 2 n-i , or

V ref <V CLK : X i =X i-1+ 2 n-i

where V CLK is the clock voltage measurement value, V ref is the generated reference voltage, X i-1 is a binary search factor of a previous iteration of the binary search, X i is a binary search factor of a current iteration, and n is a number of digital control bits.

6. The method of claim 5 , wherein said binary search is an iterative process, said method comprising:

providing a binary search table for each clock signal phase, and using said binary search table to obtain, for each iteration i, values of said binary search factors of said previous and current iterations, and an offset representing a difference of voltages between the comparator inputs, and a value representing a function of said n digital control bits.

7. The method of claim 1 , wherein calculating the duty cycle value based on the first and second matched values further comprises averaging the first and second matched values.

8. The method of claim 1 , wherein:

the first matched value has a first error value;

the second matched value has a second error value; and

the first error value is approximately equal to an inverse of the second error value.

9. The method of claim 1 , further comprising:

comparing the duty cycle value to a programmable target range;

generating code capable of modifying the duty cycle of the clock signal when the duty cycle value is outside the programmable target range.

10. A system, comprising:

a clock comparator circuit configured to:

generate a duty cycle signal having a voltage representing a duty cycle of a clock signal;

a reference voltage generator configured to:

generate, in response to a reference control signal, a reference voltage from supply voltage sources applied to the reference voltage generator; and

invert the supply voltage sources applied to the reference voltage generator in response to an applied reference polarity signal; and

a clock evaluation control circuit configured to:

adjust the reference control signal to match the reference voltage to the duty cycle signal to produce a first matched value;

adjust, while the supply voltage sources are inverted, the reference control signal to match the reference voltage to the duty cycle signal to produce a second matched value, and the clock comparator circuit is further configured to:

compare the reference voltage and the duty cycle signal with a comparator; and

swap comparator inputs into the comparator in response to an applied comparator polarity signal, and

the clock evaluation control circuit is further configured to:

adjust, while the comparator inputs are swapped, the reference voltage generated by the adjustable reference voltage generator to match the duty cycle signal to produce a third matched value;

adjust, while the supply voltage sources and the comparator inputs are swapped, the reference voltage to produce a fourth matched value; and

calculate a duty cycle value based on the first, second, third, and fourth matched values.

11. The system of claim 10 , wherein the clock comparator circuit has a low pass filter to generate the duty cycle signal.

12. The system of claim 11 , wherein the clock evaluation control circuit is further configured to perform a binary search to adjust the reference voltage to match the duty cycle signal.

13. The system of claim 12 , wherein the clock evaluation control circuit is further configured to:

apply the comparator polarity signal and the reference polarity signal to produce multiple clock signal phases representing different circuit configurations,

produce a phase clock measurement for each circuit configuration; and

average the phase clock measurements to approximate a clock voltage measurement value, and

perfrom the binary search to match the reference voltage to the clock voltage measurement value.

14. The system of claim 13 , wherein to perform said binary search, said clock evaluation circuit is configured to evaluate one of:

V ref >V CLK : X i =X i-1− 2 n-i , or

V ref <V CLK : X i =X i-1+ 2 n-i

where V CLK is the clock voltage measurement value, V ref is the generated reference voltage, X i-1 is a binary search factor of a previous iteration of the binary search, X i is a binary search factor of a current iteration, and n is a number of digital control bits.

15. The system of claim 14 , wherein said binary search is an iterative process, said clock evaluation circuit further comprising:

a binary search table for each clock signal phase, said clock evaluation circuit using said binary search table to obtain, for each iteration i, values of said binary search factors of said previous and current iterations, and an offset representing a difference of voltages between the comparator inputs, and a value representing a function of said n digital control bits.

16. The system of claim 10 , wherein the reference voltage generator:

further comprises an R-2R resistor ladder having a first voltage source and drain and a second voltage source and drain; and

is further configured to switch between the first voltage source and drain and the second voltage source and drain in response to an inverted reference polarity signal.

17. The system of claim 10 , further comprising a clock adjustment circuit configured to:

compare the duty cycle signal to a programmable target range; and

generate code capable of modifying the duty cycle of the clock signal when the duty cycle value is outside the programmable target range.