Electronic device and clock rates controlling method of overclocking operation

1. An electronic device, comprising:

a central processing unit (CPU) used for over clocking operating;

a temperature sensing element coupled with the central processing unit and used for sensing a temperature of the central processing unit operated in an over-clocked state wherein a clock rate of the over-clocked state is higher than a normal clock rate; and

a control circuit coupled with the temperature sensing element and the central processing unit and configured to control the central processing unit to enter an idle mode when the temperature of the central processing unit operated in the over-clocked state is higher than a first threshold temperature,

wherein the control circuit is further configured to control the control processing unit to return to a normal mode when the central processing unit is at the idle mode and the temperature of the central processing unit is lower than a second threshold temperature,

wherein the first threshold temperature is higher than the second threshold temperature, and a clock rate of the central processing unit at the idle mode is the clock rate of the over-clocked state and equal to a clock rate of the central processing unit at the normal mode.

2. The electronic device according to claim 1 , wherein the control circuit comprises:

an embedded controller, coupled with the temperature sensing element and used for determining whether the temperature of the central processing unit is higher than the first threshold temperature; and

a chipset coupled with the embedded controller and the central processing unit,

wherein when the temperature of the central processing unit is higher than the first threshold temperature, the embedded controller sends a pause signal to the chipset, and the chipset controls the central processing unit to enter the idle mode when the chipset receives the pause signal,

when the central processing unit is at the idle mode and the temperature of the central processing unit is lower than the second threshold temperature, the embedded controller stops sending the pause signal to the chipset, and the chipset controls the central processing unit to return to operate at the normal mode when the chipset does not receive the pause signal.

3. The electronic device according to claim 2 , wherein the chipset does not respond to part or all of peripheral devices of the electronic device when the chipset receives the pause signal.

4. The electronic device according to claim 1 , further comprising:

a triggering element coupled to the control circuit and used for receiving an operation instruction and generating a triggering signal according to the operation mode,

wherein when the control circuit receives the triggering signal, the control circuit controls the central processing unit to enter the idle mode or return to operate at the normal mode according to the triggering signal.

5. The electronic device according to claim 1 , further comprising:

a display coupled with the control circuit,

wherein the control circuit controls the display to display the temperature of the central processing unit.

6. A method for controlling an over clocking operation, applied to an electronic device with a central processing unit, wherein the CPU over clocking operates, the method comprising:

sensing a temperature of the central processing unit operated in an over-clocked state, wherein a clock rate of the over-clocked state is higher than a normal clock rate;

controlling the central processing unit to enter an idle mode when the temperature of the central processing unit operated in the over-clocked state is higher than a first threshold temperature; and

controlling the central processing unit to return to operate at a normal mode when the central processing unit is at the idle mode and the temperature of the central processing unit is lower than a second threshold temperature,

wherein the first threshold temperature is higher than the second threshold temperature and a clock rate of the central processing unit at the idle mode is the clock rate of the over-clocked state and equal to a clock rate of the central processing unit at the normal mode.

7. The method for controlling an over clocking operation according to claim 6 , wherein the electronic device includes an embedded controller and a chipset, and the step of controlling the central processing unit to enter the idle mode comprises:

sending a pause signal to the chipset by the embedded controller; and

controlling the central processing unit to enter the idle mode by the chipset when the chipset receives the pause signal,

wherein the step of controlling the central processing unit to return to operate at the normal mode comprises:

stopping sending the pause signal to the chipset by the embedded controller; and

controlling the central processing unit to return to operate at the normal mode by the chipset when the chipset does not receive the pause signal.

8. The method for controlling an over clocking operation according to claim 7 , wherein the step of controlling the central processing unit to enter the idle mode further comprises:

controlling the chipset to not respond to part or all of the peripheral devices of the electronic device.

9. The method for controlling an over clocking operation according to claim 6 , further comprising:

receiving an operation instruction;

generating a triggering signal according to the operation mode; and

controlling the central processing unit to enter the idle mode or return to operate at the normal mode according to the triggering signal.

10. The method for controlling an over clocking operation according to claim 6 , further comprising:

displaying the temperature of the central processing unit at the display of the electronic device or an external display coupled with the electronic device.