Methods of forming vertical cell semiconductor devices with single-crystalline channel structures

1. A method of fabricating a semiconductor device, the method comprising:

forming alternating interlayer insulating layers and sacrificial layers on a substrate;

forming a first capping layer on the interlayer insulating layers and the sacrificial layers;

forming a channel hole passing through the first capping layer, the interlayer insulating layers and the sacrificial layers to expose a first portion of the substrate;

forming a dielectric pattern conforming to a wall of the channel hole;

forming an amorphous channel active pattern conforming to the dielectric pattern and the exposed first portion of the substrate;

forming a channel core pattern in a space defined by the amorphous channel active pattern;

forming an amorphous silicon layer on the first capping layer and the amorphous channel active pattern;

forming a mask pattern on the amorphous silicon layer and the amorphous channel active pattern;

forming an insulating barrier layer on the mask pattern;

forming a metal catalytic layer on the insulating barrier layer; and

annealing to change the amorphous silicon layer and the amorphous channel active pattern into a single-crystalline silicon layer and a single-crystalline channel active pattern, respectively.

2. The method of claim 1 , wherein the mask pattern exposes a portion of the amorphous silicon layer.

3. The method of claim 1 :

wherein forming the insulating barrier layer on the mask pattern is preceded by etching the amorphous silicon layer to form an amorphous silicon pattern having a side wall aligned with a side wall of mask pattern and to expose a portion of the first capping layer; and

wherein forming the insulating barrier layer on the mask pattern comprises forming the insulating barrier layer on the side wall of the amorphous silicon pattern and the exposed portion of the first capping layer.

4. The method of claim 1 :

wherein forming an amorphous silicon layer on the first capping layer and the amorphous channel active pattern is preceded by forming an amorphous channel pad pattern on the amorphous channel active pattern;

wherein forming an amorphous silicon layer on the first capping layer and the amorphous channel active pattern comprises forming the amorphous silicon layer on the amorphous channel pad pattern; and

wherein annealing to change the amorphous silicon layer and the amorphous channel active pattern into a single-crystalline silicon layer and a single-crystalline channel active pattern, respectively, comprises annealing to change the amorphous silicon layer, the amorphous channel active pattern and the amorphous channel pad pattern into a single-crystalline silicon layer, a single-crystalline channel active pattern, and a single-crystalline channel pad pattern, respectively.

5. The method of claim 4 , wherein forming the amorphous channel pad pattern comprises:

recessing an upper portion of the channel core pattern in the channel hole to form a channel pad space bounded by the amorphous channel active pattern and a top surface of the recessed channel core pattern; and

forming the amorphous channel pad pattern in the channel pad space.

6. The method of claim 1 , further comprising forming a metal silicide layer by siliciding a part of the amorphous silicon layer in contact with the metal catalytic layer.

7. The method of claim 1 , further comprising:

removing the metal catalytic layer;

removing the single-crystalline silicon layer;

forming a second capping layer on the single-crystalline channel pad pattern;

forming a trench passing through the second capping layer, the interlayer insulating layers, and the sacrificial layers, and exposing a second portion of the substrate;

forming word line spaces by removing the sacrificial layers through the trench;

forming word lines in the word line spaces; and

forming a device isolation pattern in the trench.

8. The method of claim 1 , further comprising:

forming a trench vertically isolating parts of upper surfaces of the interlayer insulating layers, and parts of upper surfaces of the sacrificial layers; and

forming a line isolation pattern in the trench.

9. The method of claim 1 , wherein a metal concentration in a portion of the single-crystalline channel active pattern proximate the substrate is greater than metal concentrations in portions of the single-crystalline channel active pattern further displaced from the substrate.

10. The method of claim 9 , wherein the metal concentration in the portion of the single-crystalline channel active pattern proximate the substrate is less than or equal to about 10 19 /cm 2 .

11. The method of claim 1 , further comprising forming a crystal growth layer on the exposed substrate in the channel hole using an epitaxial growth process prior to forming the amorphous channel active pattern and the single-crystalline channel active pattern.

12. The method of claim 11 , wherein the amorphous channel active pattern and the single-crystalline channel active pattern are formed in direct contact with the crystal growth layer.

13. A method of fabricating a semiconductor device, the method comprising:

forming a stacked structure of alternating interlayer insulating layers and sacrificial layers on a substrate;

forming a channel hole vertically passing through the stacked structure and exposing a portion of the substrate;

forming a channel structure including amorphous silicon in the channel hole;

forming an amorphous silicon region on the channel structure;

forming a metal catalytic layer on the amorphous silicon region;

annealing to change the amorphous silicon and the channel structure to single-crystalline silicon using a metal induced crystallization that proceeds from the amorphous silicon region to the channel structure;

removing the metal catalytic layer;

removing the crystallized silicon region prior to forming the bit line plug and the bit line; and

forming a bit line plug and a bit line on the channel structure after removing the crystallized silicon region.

14. The method of claim 13 , further comprising:

removing portions of the sacrificial layers to form word line spaces between the insulating layers; and

forming word lines in the word line spaces.

15. A method of fabricating a semiconductor device, the method comprising:

forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate;

forming an amorphous silicon layer conforming to an inner wall of the hole;

forming a silicon region on the amorphous silicon layer;

metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole;

removing the silicon region;

removing portions of the sacrificial layers to form word line spaces; forming word lines in the word line spaces; and

forming a bit line electrically coupled to the channel structure.

16. The method of claim 15 , wherein metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole comprises:

forming a metal catalytic layer on the silicon region; and

annealing to metal induced crystallize the amorphous silicon pattern via the silicon region.