Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.
1. A method for fabricating semiconductor device, comprising:
providing a substrate having a first region and a second region defined thereon;
forming a plurality of fin-shaped structures on the substrate;
forming a gate layer on the fin-shaped structures;
forming a material layer on the gate layer;
patterning the material layer for forming sacrificial mandrels on the gate layer in the first region;
forming sidewall spacers adjacent to the sacrificial mandrels;
forming a dielectric layer on the sidewall spacers and the sacrificial mandrels;
planarizing the dielectric layer, the sidewall spacers, and the sacrificial mandrels so that the top surfaces of the sidewall spacers and the sacrificial mandrels are even with the top surface of the dielectric layer;
removing the sacrificial mandrels and the dielectric layer;
forming a patterned mask on the second region, wherein the patterned mask is not formed by sidewall image transfer (SIT) process; and
utilizing the patterned mask and the sidewall spacers to remove part of the gate layer until reaching the bottom of the gate layer.
2. The method of claim 1 , wherein the gate layer comprises amorphous silicon or polysilicon.
3. The method of claim 1 , wherein the material layer comprises amorphous silicon.
4. The method of claim 1 , further comprising forming a silicon nitride layer and a silicon oxide layer on the gate layer before forming the material layer.
5. The method of claim 4 , further comprising utilizing the sidewall spacers to remove part of the silicon nitride layer, part of the silicon oxide layer, and part of the gate layer.
6. The method of claim 1 , further comprising trimming the sidewall spacers before forming the patterned mask.
7. The method of claim 1 further comprising trimming the sidewall spacers after forming the patterning mask.
8. The method of claim 1 , further comprising performing a chemical mechanical polishing (CMP) process to planarize the gate layer before forming the material layer.