Electrostatic discharge protection circuit
View Patent ↗A device comprises a high voltage N well and a high voltage P well over an N+ buried layer, a high voltage P-type implanted region in the high voltage N well, a first N+ region over the high voltage P-type implanted region and a P+ region and a second N+ region over the high voltage P well.
1. A device comprising:
a high voltage N well and a high voltage P well over an N+ buried layer;
a high voltage P-type implanted region in the high voltage N well;
a first N+ region over the high voltage P-type implanted region; and
a P+ region and a second N+ region over the high voltage P well, wherein the high voltage N well, the high voltage P well, the N+ buried layer, the high voltage P-type implanted region, the first N+ region, the P+ region and the second N+ region form a protection structure comprising a silicon-controlled rectifier and a diode connected in series, wherein an anode of the diode is connected to the silicon-controlled rectifier.
2. The device of claim 1 , further comprising:
a first isolation region between the first N+ region and the P+ region; and
a second isolation region between the P+ region and the second N+ region.
3. The device of claim 1 , wherein:
the diode is a reverse diode.
4. The device of claim 1 , wherein the silicon-controlled rectifier comprises a PNP transistor and an NPN transistor, and wherein:
the PNP transistor has a base interconnected with a collector of the NPN transistor and a collector interconnected with a base of the NPN transistor.
5. The device of claim 1 , wherein:
the diode comprises a cathode formed in the first N+ region and an anode formed in the high voltage P-type implanted region.
6. A structure comprising:
a N+ buried layer;
a high voltage N well disposed on the N+ buried layer;
a high voltage P type implanted region disposed on the high voltage N well and partially within the high voltage N well;
a first N+ region disposed on the high voltage P type implanted region;
a high voltage P well disposed on the N+ buried layer;
a second N+ region disposed on the high voltage P well; and
a P+ region disposed on the high voltage P well, wherein the high voltage N well, the high voltage P well, the N+ buried layer, the high voltage P type implanted region, the first N+ region, the P+ region and the second N+ region form a protection structure comprising a silicon-controlled rectifier and a diode connected in series, wherein an anode of the diode is connected to the silicon-controlled rectifier.
7. The structure of claim 6 further comprising a first isolator, wherein the first N+ region and the P+ region are on opposite sides of the first isolator.
8. The structure of claim 6 further comprising a second isolator, wherein the second N+ region and the P+ region are on opposite sides of the second isolator.
9. The structure of claim 6 , wherein:
the first N+ region and the high voltage P type implanted region form a reverse diode having a breakdown voltage.
10. The structure of claim 6 , wherein:
the high voltage P type implanted region, the high voltage N well and the high voltage P well form a bipolar PNP transistor; and
the high voltage N well, the high voltage P well and the second N+ region form a bipolar NPN transistor.
11. The structure of claim 10 , wherein:
the bipolar PNP transistor and the bipolar NPN transistor form the silicon-controlled rectifier.
12. A device comprising:
a diode having a cathode formed in a first N+ region and an anode formed in a high voltage P-type implanted region, wherein the high voltage P-type implanted region is in a high voltage N well over an N+ buried layer; and
a silicon-controlled rectifier comprising a PNP transistor and an NPN transistor, wherein the PNP transistor comprises:
a base interconnected with a collector of the NPN transistor;
a collector interconnected with a base of the NPN transistor; and
an emitter interconnected with the anode of the diode.
13. The device of claim 12 , wherein:
the base of the PNP transistor is formed in the high voltage N well;
the collector of the PNP transistor is formed in a high voltage P well and a P+ region, wherein the P+ region is over the high voltage P well; and
an emitter of the NPN transistor is formed in a second N+ region over the high voltage P well.
14. The device of claim 13 , wherein:
the high voltage P well is over the N+ buried layer.
15. The device of claim 14 , further comprising:
a first isolation region having a first portion over the high voltage N well and a second portion over the high voltage P well; and
a second isolation region over the high voltage P well.
16. The device of claim 15 , wherein:
the first N+ region and the P+ region are separated by the first isolation region; and
the P+ region and the second N+ region are separated by the second isolation region.
17. The device of claim 12 , wherein:
the silicon-controlled rectifier and the diode are connected series.
18. The device of claim 17 , wherein:
the diode is a reverse diode.