Noise cancellation apparatus and method
A noise cancellation structure comprises a trans-impedance stage couple to an output of a mixer of a receiver and a noise cancellation stage connected in parallel with the trans-impedance stage, wherein the noise cancellation stage comprises a first adjustable resistor and a second adjustable resistor connected in series with the first adjustable resistor, wherein the first adjustable resistor and the second adjustable resistor are configured such that the first adjustable resistor has a first resistance variation portion and the second adjustable resistor has a second resistance variation portion equal to the first resistance variation in an opposite direction and a magnitude of the first resistance variation is so selected that differential mode second-order noise and common mode second-order noise cancel each other.
1. An apparatus comprising:
a trans-impedance stage coupled to an output of a mixer of a receiver;
a noise cancellation stage connected in parallel with the trans-impedance stage, wherein the noise cancellation stage comprises:
a first adjustable resistor; and
a second adjustable resistor connected in series with the first adjustable resistor, wherein the first adjustable resistor and the second adjustable resistor are configured such that:
the first adjustable resistor has a first resistance variation and the second adjustable resistor has a second resistance variation equal to the first resistance variation in an opposite direction; and
the first resistance variation is so selected that differential mode second-order noise and common mode second-order noise cancel each other; and
a buffer having an output connected to a common node of the first adjustable resistor and the second adjustable resistor.
2. The apparatus of claim 1 , wherein:
the trans-impedance stage comprises two common gate transistors.
3. The apparatus of claim 1 , wherein:
the first adjustable resistor comprises a first fixed portion and a first adjustable portion; and
the second adjustable resistor comprises a second fixed portion and a second adjustable portion.
4. The apparatus of claim 3 , wherein:
the first fixed portion is of a resistance value equal to that of the second fixed portion; and
the first adjustable portion is of a variable resistance value equal to that of the second adjustable portion.
5. The apparatus of claim 1 , further comprising:
a common mode feedback loop stage connected in parallel with the noise cancellation stage, wherein the common mode feedback loop stage is configured to regulate an output voltage of the trans-impedance stage in response to a reference voltage.
6. The apparatus of claim 5 , wherein:
the buffer is coupled between the reference voltage and a common node of the first adjustable resistor and the second adjustable resistor, wherein the buffer provides a low impedance output.
7. The apparatus of claim 6 , wherein:
the buffer is configured to regulate a voltage at an output of the buffer approximately equal to the reference voltage.
8. A device comprising:
an amplifier stage having inputs connected to outputs of a receiver;
a noise reduction stage connected between two outputs of the amplifier stage, wherein the noise reduction stage comprises a first variable resistor connected in series with a second variable resistor, and wherein the first variable resistor and the second variable resistor are configured such that:
the first variable resistor has a first resistance variation and the second variable resistor has a second resistance variation equal to the first resistance variation in an opposite direction; and
the first resistance variation is so selected that differential mode noise and common mode noise cancel each other; and
a feedback loop stage connected between the two outputs of the amplifier stage, wherein an input of a buffer of the noise reduction stage is connected to an input of the feedback loop stage.
9. The device of claim 8 , wherein:
the amplifier stage is a common-gate trans-impedance amplifier.
10. The device of claim 8 , wherein:
the noise reduction stage is configured to reduce second-order noise.
11. The device of claim 8 , wherein:
the feedback loop stage is configured to stabilize an output voltage of the amplifier stage.
12. The device of claim 8 , wherein:
the noise reduction stage and the feedback loop stage are connected in parallel.
13. The device of claim 8 , wherein:
the first variable resistor and the second variable resistor are selected such that the variable resistors satisfies:
I IM2 _ DM ·R+I IM2 _ CM ·ΔR= 0
where R is a fixed portion of the first variable resistor and the second variable resistor, ΔR is a variable portion of the first variable resistor and the second variable resistor, I IM2 _ DM is an I-channel differential mode second-order component and I IM2 _ CM cm is an I-channel common mode second-order component.
14. The device of claim 8 , wherein:
the first variable resistor and the second variable resistor are selected such that the variable resistors satisfies:
I IM2 _ DM ·R+I IM2 _ CM ·ΔR= 0
where R is a fixed portion of the first variable resistor and the second variable resistor, ΔR is a variable portion of the first variable resistor and the second variable resistor, I IM2 _ DM is a Q-channel differential mode second-order component and I IM2 _ CM is a Q-channel common mode second-order component.
15. An apparatus comprising:
an amplifier stage comprising a common gate circuit;
a noise reduction stage connected between two outputs of the amplifier stage, wherein the noise reduction stage comprises a buffer, a first adjustable resistor and a second adjustable resistor, wherein an input of the buffer is connected to a reference voltage and an output of the buffer is connected to a common node of the first adjustable resistor and the second adjustable resistor; and
a feedback loop stage connected between the two outputs of the amplifier stage.
16. The apparatus of claim 15 , wherein:
the first adjustable resistor is connected in series with the second adjustable resistor, and wherein the first adjustable resistor and the second adjustable resistor are configured such that:
the first adjustable resistor has a first resistance variation and the second adjustable resistor has a second resistance variation equal to the first resistance variation in an opposite direction; and
the first resistance variation is so selected that differential mode second-order noise and common mode second-order noise cancel each other.
17. The apparatus of claim 15 , wherein:
the feedback loop stage comprises a first amplifier, a first resistor, a second resistor, a first transistor and a second transistor, and wherein:
the first amplifier has a first input connected to the reference voltage and a second input connected to a common node of the first resistor and the second resistor; and
gates of the first transistor and the second transistor are connected to an output of the first amplifier.
18. The apparatus of claim 17 , wherein:
the first transistor is connected between a supply voltage and a first output of the amplifier stage; and
the second transistor is connected between the supply voltage and a second output of the amplifier stage.
19. The apparatus of claim 17 , wherein:
the first resistor and the second resistor are connected in series between the two outputs of the amplifier stage.
20. The apparatus of claim 15 , wherein:
the buffer is configured to regulate a voltage at the common node of the first adjustable resistor and the second adjustable resistor.