IP Library › Granted Patent US 9,323,606
Granted Patent B2
US 9,323,606 · App. 14/101,368 · Granted Apr 26, 2016

Systems and methods for FAID follower decoding

Inventors: Yequn Zhang (Tucson, AZ); Yang Han (Sunnyvale, CA); Yu Chin Fabian Lim (San Jose, CA); Shu Li (San Jose, CA); Fan Zhang (Milpitas, CA); Shaohua Yang (San Jose, CA)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
G06F11/1008H03M13/09H03M13/1111H03M13/27H03M13/2957H03M13/3707H03M13/3723H03M13/3746H03M13/6331H03M13/6343H03M13/6594H03M13/41
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Quick Facts
Patent No.
US 9,323,606
App. No.
14/101,368
Granted
Apr 26, 2016
Kind
B2
Abstract

Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information. Some disclosed systems include a first data decoding circuit, a second data decoding circuit, and a data output circuit. The second data decoding circuit is coupled to the first data decoding circuit and the data output circuit. The second data decoding circuit is operable to apply a finite alphabet iterative decoding algorithm to the first decoded output to yield a second decoded output.

Claims (30)

1. A data processing system, the data processing system comprising:

a first data decoding circuit operable to apply a low density parity check decoding algorithm to a decoder input to yield a first decoded output; and

a second data decoding circuit coupled to the first data decoding circuit and a data output circuit, wherein the second data decoding circuit is operable to apply a finite alphabet iterative decoding algorithm to the first decoded output to yield a second decoded output, and wherein the second decoded output is only provided to one or both of the data output circuit or the second data decoding circuit.

2. The data processing system of claim 1 , wherein the finite alphabet iterative decoding algorithm is operable to map a variable node value into a defined map including a number of elements.

3. The data processing system of claim 2 , wherein the number of elements is a second finite number of elements; wherein the low density parity check decoding algorithm allows a first finite number of elements; wherein the finite alphabet iterative decoding algorithm allows the second finite number of elements; and wherein the second finite number is less than the first finite number.

4. The data processing system of claim 3 , wherein the second finite number is less than half of the first finite number.

5. The data processing system of claim 3 , wherein the first finite number is thirty-one, and wherein the second finite number is between nine and seventeen.

6. The data processing system of claim 5 , wherein the second finite number is nine.

7. The data processing system of claim 2 , wherein the defined map is generated by applying the finite alphabet iterative decoding algorithm to the first decoded output using a first instance of the defined map to yield a first result, applying the finite alphabet iterative decoding algorithm to the first decoded output using a second instance of the defined map to yield a second result, and selecting one of the first instance of the defined map and the second instance of the defined map based upon a comparison of the first result and the second result.

8. The data processing system of claim 7 , wherein the number of elements in the defined map is nine; and wherein applying the finite alphabet iterative decoding algorithm to the first decoded output is repeated for 3165 different instances of the defined map to yield corresponding results, and selecting the instance associated with the best of the corresponding results.

9. The data processing system of claim 2 , wherein the defined map is generated by applying the finite alphabet iterative decoding algorithm to a collection of errors around an error floor of the first decoded output using a first instance of the defined map to yield a first result, applying the finite alphabet iterative decoding algorithm to the collection of errors around the error floor of the first decoded output using a second instance of the defined map to yield a second result, and selecting one of the first instance of the defined map and the second instance of the defined map based upon a comparison of the first result and the second result.

10. The data processing system of claim 1 , the data processing system further comprises:

a data detector circuit operable to apply a data detection algorithm to a detector input to yield a detected output; and

wherein the decoder input is derived from the detector output.

11. The data processing system of claim 10 , wherein the data detection algorithm is selected from a group consisting of: a maximum a posteriori data detection algorithm, and a Viterbi data detection algorithm.

12. The data processing system of claim 1 , wherein the system is implemented as an integrated circuit.

13. The data processing system of claim 1 , wherein the data processing system is incorporated in a device selected from a group consisting of: a storage device, and a communication device.

14. A method for data processing, the method comprising:

applying a low density parity check decoding algorithm by a low density parity check decoder circuit to a decoder input to yield a first decoded output;

applying a finite alphabet iterative decoding algorithm by a finite alphabet iterative decoding circuit to the first decoded output to yield a second decoded output; and

providing the second decoded output to one or both of a data output circuit or the finite alphabet iterative decoding circuit.

15. The method of claim 14 , wherein the finite alphabet iterative decoding algorithm is operable to map a variable node value into a defined map including a number of elements.

16. The method of claim 15 , wherein the number of elements is a second finite number of elements; wherein the low density parity check decoding algorithm allows a first finite number of elements; wherein the finite alphabet iterative decoding algorithm allows the second finite number of elements; and wherein the second finite number is less than the first finite number.

17. The method of claim 16 , wherein the first finite number is thirty-one, and wherein the second finite number is nine.

18. The method of claim 15 , wherein the method further comprises:

generating the defined map by applying the finite alphabet iterative decoding algorithm to the first decoded output using a first instance of the defined map to yield a first result, applying the finite alphabet iterative decoding algorithm to the first decoded output using a second instance of the defined map to yield a second result, and selecting one of the first instance of the defined map and the second instance of the defined map based upon a comparison of the first result and the second result.

19. The method of claim 18 , wherein the second finite number is nine, and wherein applying the finite alphabet iterative decoding algorithm to the first decoded output is repeated for 3165 different instances of the defined map to yield corresponding results, and selecting the instance associated with the best of the corresponding results.

20. The method of claim 15 , wherein the method further comprises:

selecting a collection of errors around an error floor of the first decoded output; and

generating the defined map by applying the finite alphabet iterative decoding algorithm to the collection of errors around the error floor of the first decoded output using a first instance of the defined map to yield a first result, applying the finite alphabet iterative decoding algorithm to the collection of errors around the error floor of the first decoded output using a second instance of the defined map to yield a second result, and selecting one of the first instance of the defined map and the second instance of the defined map based upon a comparison of the first result and the second result.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2013
From: ZHANG, YEQUN; HAN, YANG; LIM, YU CHIN FABIN; ZHANG, FAN; YANG, SHAOHUA; LI, SHU
To: LSI CORPORATION
Reel/Frame 031746/0722 →
Continuity (2)
Provisional Application 61907170 · Nov 21, 2013
Related Publication 20150143196A1 · May 21, 2015