Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
1. A processor comprising:
a plurality of cores including a first core having:
a computation processor; and
a programmable engine coupled to the computation processor to perform address calculation and memory accesses, the programmable engine to generate sub-cache line sized non-sequential data accesses to a memory based on an access pattern to communicate sub-cache line sized data with the memory, the access pattern explicitly provided by an application, wherein the programmable engine is to store a stride access pattern data structure to be allocated for a first matrix of a matrix multiply function; and
a cache coupled to the first core, wherein data is to be transferred between the cache and the memory via a full-cache line sized transfer.
2. The processor of claim 1 , wherein the programmable engine includes an access processor, an access pattern generator, and a cache interface.
3. The processor of claim 2 , wherein the access processor is to compute memory addresses for the sub-cache line sized non-sequential data accesses and perform data format conversion.
4. The processor of claim 2 , wherein the access processor is to prepare an operand while the computation processor is to perform a computation.
5. The processor of claim 2 , wherein the access processor is to generate the sub-cache line sized non-sequential data accesses to the memory based on an indirect access pattern.
6. The processor of claim 5 , wherein the indirect access pattern comprises a sparse matrix dense vector multiplication.
7. The processor of claim 2 , wherein the access pattern generator is to generate the sub-cache line sized non-sequential data accesses to the memory based on a stride-based access pattern.
8. The processor of claim 2 , wherein the computation processor and the access processor are to be associated with a same process identifier.
9. The processor of claim 2 , wherein the programmable engine further comprises:
a stream port coupled to the computation processor, the stream port including a buffer to store ordered data accessible by the access processor and the computation processor.
10. The processor of claim 9 , wherein the buffer comprises a first port and a second port to enable the computation processor and the access processor to concurrently access the buffer.
11. The processor of claim 9 , wherein the computation processor is to allocate the stream port, map the access pattern to the stream port, and wherein the access processor is to execute a memory access handler to perform a scatter/gather operation to place the sub-cache line sized data in the stream port.
12. The processor of claim 11 , wherein the memory access handler is to receive a port value to identify the stream port and a pattern value to identify the access pattern.
13. The processor of claim 1 , wherein the computation processor is to perform data computations for the first matrix using a stream port of the access processor.
14. A system comprising:
a multicore processor having a plurality of cores including a first core having a computation processor and a programmable engine to perform address calculation and memory accesses to generate sub-cache line sized non-sequential data accesses to a memory based on an access pattern and communicate sub-cache line sized data with the memory, a first memory controller and a second memory controller, the access pattern explicitly provided by an application, wherein the programmable engine is to store a stride access pattern data structure to be allocated for a first matrix of a matrix multiply function; and
the memory coupled to the multicore processor, the memory including a first plurality of channels associated with the first memory controller and a second plurality of channels associated with the second memory controller.
15. The system of claim 14 , wherein each of the first plurality of channels are to be used to perform scatter/gather operations.
16. The system of claim 14 , wherein the memory is to support cache line size data transfer and sub-cache line size data transfer.
17. A non-transitory machine-accessible storage medium including instructions that when executed cause a system to perform a method comprising:
performing, in a programmable engine coupled to a computation processor of a core, address calculation and memory accesses;
generating, in the programmable engine, sub-cache line sized non-sequential data accesses to a memory based on an access pattern;
storing, in the programmable engine, a stride access pattern data structure to be allocated for a first matrix of a matrix multiply function; and
communicating sub-cache line sized data with the memory, the access pattern explicitly provided by an application, wherein the memory supports cache line size data transfer and sub-cache line size data transfer.
18. The non-transitory machine-accessible storage medium of claim 17 , wherein the method further comprises:
computing, by an access processor of the programmable engine, memory addresses for the sub-cache line sized non-sequential data accesses; and
performing, in the access processor, data format conversion.
19. The non-transitory machine-accessible storage medium of claim 18 , wherein the method further comprises preparing, by the access processor, an operand while the computation processor performs a computation.