Packaging method
The present invention relates to a packaging method including the steps: a cementing layer is formed on a carrier board; the functional sides of chips and passive devices are attached to the cementing layer; a sealing material layer is formed on the side of the carrier board to which the chips and the passive devices are attached, and packaging and curing are performed; and the carrier board and the cementing layer are removed. Compared to the prior art, the system-level fan-out wafer packaging method claimed by the present invention first integrates chips and passive devices and then packages the chips and the passive devices together, thereby forming a final packaged product having not single-chip functionality but integrated-system functionality. Compared to current system-level packaging, highly integrated wafer-level packaging reduces such interfering factors as system-internal electric resistance and inductance, and accommodates the growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.
1. A high-density system-level chip packaging method, comprising:
forming an adhesive layer on a carrier board directly, where a shape and position of the adhesive layer correspond to shapes of functional surfaces of units to be packaged and positions on the carrier board where the units to be packaged are to be attached, respectively, so that the units to be packaged are attached according to the position of the adhesive layer in subsequent processes;
affixing at least one chip and at least one periphery circuit on the adhesive layer with functional surfaces of the at least one chip and the at least one periphery circuit-attached to the adhesive layer, where one unit to be packaged comprises one chip and one periphery circuit;
forming a sealing material layer on a surface of the carrier board to which the at least one chip and the at least one periphery circuit are attached and performing packaging and curing, wherein a plurality of grooves are formed on the sealing material layer in positions corresponding to intervals between the units to be packaged, and the plurality of grooves form a plurality of closed loops each of which is around at least one of the units to be packaged; and
removing the carrier board and the adhesive layer entirely.
2. The method according to claim 1 , wherein when a plurality of chips are attached on the adhesive layer, the sealing material layer is filled into spaces between the plurality of chips; when the at least one chip and the at least one periphery circuit are attached on the adhesive layer, the sealing material layer is filled into spaces between the at least one chip and the at least one periphery circuit; and when a plurality of periphery circuits are attached on the adhesive layer, the sealing material layer is filled into spaces between the plurality of periphery circuits.
3. The method according to claim 1 , wherein the at least one periphery circuit comprises a capacitor, a resistor or an inductor.
4. The method according to claim 1 , wherein the sealing material layer is made of epoxy resin.
5. The method according to claim 1 , wherein the sealing material layer is formed on the at least one chip and the at least one periphery circuit-by transfer molding, compressing or printing.
6. The method according to claim 1 , wherein the adhesive layer is made of ultraviolet adhesive.
7. The method according to claim 1 , wherein an alignment part is disposed on the carrier board.
8. The method according to claim 7 , wherein a shape and size of the alignment part are determined by a plurality of location parts.
9. The method according to claim 8 , wherein the plurality of location parts are cruciform, dual cruciform, star-shaped, L-shaped, dual-L-shaped or point-shaped.
10. The method according to claim 1 , wherein the adhesive layer comprises a plurality of adhesive blocks separated from one another.
11. The method according to claim 10 , wherein at least two of the plurality of adhesive blocks have different shapes.
12. The method according to claim 10 , wherein the plurality of adhesive blocks are square, rectangular or circular.
13. The method according to claim 10 , wherein the plurality of adhesive blocks are arranged on the carrier block in matrix.
14. The method according to claim 13 , wherein the plurality of adhesive blocks are spaced at a same interval on the carrier board.
15. The method according to claim 10 , wherein an interval between the plurality of adhesive blocks is determined according to the arrangement scheme of the units to be packaged.
16. The method according to claim 1 , wherein removing the carrier board and the adhesive layer comprises:
removing the adhesive layer;
separating the carrier board from the functional surfaces of the at least one chip and the at least one periphery circuit; and
cleaning the functional surfaces of the at least one chip and the at least one periphery circuit.
17. The method according to claim 1 , wherein the at least one chip comprises a plurality of different chips.
18. The method according to claim 1 , wherein the carrier board is made of glass.
19. The method according to claim 1 , further comprising:
forming a metal re-wiring layer on the exposed functional surfaces of the at least one chip and the at least one periphery circuit;
forming a protective film on a surface of the metal re-wiring layer;
forming an opening which exposes the surface of the metal re-wiring layer in the protective film layer;
forming a sub-ball metal layer which is connected with the metal re-wiring layer in the opening; and
forming a metal welding ball on a surface of the sub-ball metal layer.