IP Library › Granted Patent US 9,324,603
Granted Patent B2
US 9,324,603 · App. 13/967,558 · Granted Apr 26, 2016

Semiconductor structures with shallow trench isolations

Inventors: Shin-Yeu Tsai (Zhubei, TW); Chia-Hui Lin (Dajia Township, Taichung County, TW); Ching-Yu Chen (Keelung, TW); Chui-Ya Peng (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/76224H01L21/76229
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Quick Facts
Patent No.
US 9,324,603
App. No.
13/967,558
Granted
Apr 26, 2016
Kind
B2
Abstract

A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.

Claims (32)

1. A method comprising:

disposing an insulating material within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate, wherein at least two trenches of the plurality of the trenches have different depths;

forming, in one operation, a first layer having a substantially flat surface, over the insulating material; and

removing the first layer and the insulating material;

wherein a portion of the first layer is etched, a remaining portion of the first layer and the insulating material are removed by a chemical mechanical polishing (CMP) process, and the portion of the first layer is thicker than a percentage of the remaining portion of the first layer.

2. The method of claim 1 , wherein the first layer is formed by a spin-coating process.

3. The method of claim 1 , wherein the insulating material comprises oxide.

4. The method of claim 1 , wherein the first layer comprises a layer of photoresist.

5. The method of claim 1 , wherein removing the first layer and the insulating material is performed by at least one of a chemical mechanical polishing (CMP) process, an etching process, a sputter process, a laser process and combinations thereof.

6. The method of claim 1 , wherein the first layer and the insulating material have a similar etch rate.

7. The method of claim 1 , wherein the first layer and the insulating material are removed by a chemical mechanical polishing (CMP) process in one operation.

8. The method of claim 1 , wherein the first layer comprises a layer of spin-on glass (SOG).

9. The method of claim 1 , wherein the first layer is a single layer having a same type of material.

10. The method of claim 1 , wherein the first layer is formed over the insulating material before disposing of another material on the insulating material.

11. The method of claim 1 , wherein the first layer is formed over the insulating material without another material there between.

12. The method of claim 1 , wherein the first layer is formed in contact with the insulating material over an entirety of the insulating material.

13. A method comprising:

coating, in one operation, an insulating layer with a first layer having a substantially flat surface by a spin-coating process; and

removing the first layer and the insulating layer;

wherein the insulating layer fills a plurality of trenches on a semiconductor substrate and covers the semiconductor substrate, and

at least two of the plurality of trenches have different depths;

wherein a portion of the first layer is etched, a remaining portion of the first layer and the insulating layer are removed by a chemical mechanical polishing (CMP) process, and the portion of the first layer is thicker than a percentage of the remaining portion of the first layer.

14. The method of claim 13 , wherein a material of the insulating layer comprises oxide.

15. The method of claim 13 , wherein the first layer comprises a layer of photoresist.

16. The method of claim 13 , wherein removing the first layer and the insulating layer is performed by at least one of a chemical mechanical polishing (CMP) process, an etching process, a sputter process, a laser process and combinations thereof.

17. The method of claim 13 , wherein the first layer and the insulating layer have a similar etch rate.

18. The method of claim 13 , wherein the first layer and the insulating layer are removed by a chemical mechanical polishing (CMP) process in one operation.

19. The method of claim 13 , wherein the first layer comprises a layer of spin-on glass (SOG).

20. The method of claim 13 , wherein the first layer is a single layer having a same type of material.

21. The method of claim 13 , wherein the first layer is formed over the insulating layer before disposing of another material on the insulating layer.

22. The method of claim 13 , wherein the first layer is formed over the insulating layer without another material there between.

23. The method of claim 13 , wherein the first layer is formed in contact with the insulating layer over an entirety of the insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2013
From: TSAI, SHIN-YEU; LIN, CHIA-HUI; CHEN, CHING-YU; PENG, CHUI-YA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Reel/Frame 031017/0188 →
Continuity (1)
Related Publication 20150048475A1 · Feb 19, 2015