Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same
Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.
1. A method of fabricating a semiconductor chip, the method comprising:
forming a plurality of grooves in a backside of a semiconductor wafer having a plurality of semiconductor chips;
forming a plurality of non-conductive material patterns in respective ones of the plurality of grooves, wherein the non-conductive material patterns fill the grooves and the surfaces of the non-conductive material patterns are coplanar with the backside of the semiconductor wafer; and
separating the plurality of semiconductor chips including the non-conductive material patterns.
2. The method of claim 1 , wherein forming the plurality of grooves includes:
attaching a jig having a plurality of openings that expose respective ones of the semiconductor chips to a backside surface of the semiconductor wafer;
etching a backside of the semiconductor wafer using the jig as an etch mask; and
detaching the jig from the semiconductor wafer.
3. The method of claim 2 , wherein the backside of the semiconductor wafer is etched using at least one of a physical etching process and a chemical etching process.
4. The method of claim 1 , wherein forming the plurality of non-conductive material patterns includes:
coating a non-conductive material layer on a backside surface of the semiconductor wafer to fill the grooves; and
grinding the non-conductive material layer and the semiconductor wafer.
5. The method of claim 4 , wherein the non-conductive material layer comprises a material having substantially the same grinding rate as the semiconductor wafer.
6. The method of claim 5 , wherein the non-conductive material layer is formed of an epoxy type polymer material or a silicon resin material.
7. The method of claim 4 , wherein grinding the non-conductive material layer and the semiconductor wafer is performed to expose the backside surface of the semiconductor wafer.
8. The method of claim 1 , wherein forming a plurality of grooves is performed to form an arch-shaped grooves.
9. A method of fabricating a semiconductor package, the method comprising:
forming a plurality of grooves in a backside of a semiconductor wafer having a plurality of semiconductor chips;
forming a plurality of non-conductive material patterns in respective ones of the plurality of grooves, wherein the non-conductive material patterns fill the grooves and the surfaces of the non-conductive material patterns are coplanar with the backside of the semiconductor wafer;
separating the plurality of semiconductor chips including the non-conductive material patterns;
attaching one of the separated semiconductor chips to a substrate;
electrically connecting the attached semiconductor chip to the substrate through wires; and
forming a mold resin material encapsulating the attached semiconductor chip and the wires.
10. The method of claim 9 , wherein forming the plurality of grooves includes:
attaching a jig having a plurality of openings that expose respective ones of the semiconductor chips to a backside surface of the semiconductor wafer;
etching a backside of the semiconductor wafer using the jig as an etch mask; and
detaching the jig from the semiconductor wafer.
11. The method of claim 10 , wherein the backside of the semiconductor wafer is etched using at least one of a physical etching process and a chemical etching process.
12. The method of claim 9 , wherein forming the plurality of non-conductive material patterns includes:
coating a non-conductive material layer on a backside surface of the semiconductor wafer to fill the grooves; and
grinding the non-conductive material layer and the semiconductor wafer.
13. The method of claim 12 , wherein the non-conductive material layer comprises a material having substantially the same grinding rate as the semiconductor wafer.
14. The method of claim 13 , wherein the non-conductive material layer is formed of an epoxy type polymer material or a silicon resin material.
15. The method of claim 12 , wherein grinding the non-conductive material layer and the semiconductor wafer is performed to expose the backside surface of the semiconductor wafer.
16. The method of claim 9 , wherein forming a plurality of grooves is performed to form an arch-shaped grooves.