Data receivers and methods of implementing data receivers in an integrated circuit

1. A data receiver implemented in an integrated circuit, the data receiver comprising:

an input receiving a data signal;

a phase locked loop configured to generate a reference clock signal;

a first equalization circuit configured to receive the data signal, wherein the first equalization circuit is used to receive data of the data signal;

a first register coupled to an output of the first equalization circuit;

a first phase interpolator configured to receive the reference clock signal, wherein the first phase interpolator is configured to control the first register using a first clock signal;

a second equalization circuit configured to receive the data signal;

a second register coupled to an output of the second equalization circuit; and

a second phase interpolator configured to receive the reference clock signal, wherein the second phase interpolator is configured to control the second register using a second clock signal that is different than the first clock signal, wherein the first clock signal is generated separately from the second clock signal, and wherein the second phase interpolator enables adjusting a clock phase offset associated with drifting of the reference clock signal;

wherein the second equalization circuit is different than the first equalization circuit; and

wherein the first phase interpolator enables a first function of said controlling the first register using the first clock signal while the second phase interpolator enables a second function of said adjusting the clock phase offset using the second clock signal.

2. The data receiver of claim 1 wherein the first equalization circuit comprises a linear equalization circuit.

3. The data receiver of claim 2 wherein the linear equalization circuit comprises a long-tail correcting continuous time linear equalization circuit.

4. The data receiver of claim 1 wherein the first equalization circuit is coupled to a decision feedback equalization circuit.

5. The data receiver of claim 4 wherein the decision feedback equalization circuit comprises an unrolling decision feedback equalization circuit.

6. The data receiver of claim 1 wherein the second equalization circuit comprises a continuous time linear equalization circuit.

7. The data receiver of claim 6 wherein the continuous time linear equalization circuit comprises a channel inversion continuous time linear equalization circuit.

8. A data receiver implemented in an integrated circuit, the data receiver comprising:

an input receiving a data signal;

a phase locked loop configured to generate a reference clock signal;

a first linear equalization circuit coupled to the input;

a first clock and data recovery circuit used to receive data of the data signal, wherein the first clock and data recovery circuit controls a first phase interpolator configured to receive the reference clock signal, wherein the first phase interpolator generates a first clock signal controlling a first register coupled to an output of the first linear equalization circuit, and wherein the first clock and data recovery circuit enables a first function of receiving the data of the data signal using the first clock signal;

a second linear equalization circuit coupled to the input, wherein the second linear equalization circuit is different than the first linear equalization circuit; and

a second clock and data recovery circuit used to adjust a clock phase offset associated with drifting of the reference clock, wherein the second clock and data recovery circuit controls a second phase interpolator configured to receive the reference clock signal, wherein the second phase interpolator generates a second clock signal controlling a second register coupled to an output of the second linear equalization circuit, wherein the second clock and data recovery circuit enables a second function of adjusting the clock phase offset, while

the first clock and data recovery circuit enables the first function of receiving the data of the data signal, using the second clock signal that is different than the first clock signal, and wherein the first clock signal is generated separately from the second clock signal.

9. The data receiver of claim 8 wherein the first clock and data recovery circuit used to receive data of the data signal uses major crossings between data bits to extract clock timing information in the data signal.

10. The data receiver of claim 9 wherein the first clock and data recovery circuit comprises an Alexander clock and data recovery circuit.

11. The data receiver of claim 9 wherein the second clock and data recovery circuit used to adjust a clock phase offset uses minor crossings between data bits to extract clock timing information in the data signal.

12. The data receiver of claim 11 wherein the second clock and data recovery circuit used to adjust a clock phase offset comprises a Mueller-Muller circuit.

13. The data receiver of claim 8 wherein the first linear equalization circuit comprises a long-tail continuous time linear equalization circuit.

14. The data receiver of claim 13 wherein the second linear equalization circuit comprises a channel inversion continuous time linear equalization circuit.

15. A method of implementing a data receiver in an integrated circuit, the method comprising:

receiving a data signal;

configuring a phase locked loop to generate a reference clock signal;

coupling the data signal to a first linear equalization circuit;

implementing a first clock and data recovery circuit in the data receiver to recover data of the data signal, wherein the first clock and data recovery circuit controls a first phase interpolator configured to receive the reference clock signal, wherein the first phase interpolator generates a first clock signal controlling a first register coupled to an output of the first linear equalization circuit, and wherein the first clock and data recovery circuit enables a first function of receiving the data signal using the first clock signal;

coupling the data signal to a second linear equalization circuit, wherein the second linear equalization circuit is different than the first linear equalization circuit; and

implementing a second clock and data recovery circuit in the data receiver to adjust a clock phase offset associated with drifting of the reference clock signal, wherein the second clock and data recovery circuit controls a second phase interpolator configured to receive the reference clock signal, wherein the second phase interpolator generates a second clock signal controlling a second register coupled to an output of the second linear equalization circuit, wherein the second clock and data recovery circuit enables a second function of adjusting the clock phase offset, the first clock and data recovery circuit enables the first function of receiving the data of the data signal, using the second clock signal that is different than the first clock signal, and wherein the first clock signal is generated separately from the second clock signal.

16. The method of claim 15 wherein coupling the data signal to a first linear equalization circuit comprises coupling the data signal to a long-tail correcting continuous time linear equalization circuit.

17. The method of claim 16 wherein coupling the data signal to a second linear equalization circuit comprises coupling the data to a channel inversion continuous time linear equalization circuit.

18. The method of claim 17 wherein the second clock and data recovery circuit is different than the first clock and data recovery circuit.

19. The method of claim 15 wherein implementing a first clock and data recovery circuit to recover the data of the data signal comprises implementing an Alexander clock and data recovery circuit.

20. The method of claim 15 wherein implementing a second clock and data recovery circuit to adjust a clock phase offset comprises implementing a Mueller-Muller clock and data recovery circuit.