Enable and select inputs operate combinational logic parallel scan paths
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.
1. An integrated circuit comprising:
A. functional combinational logic that includes functional flip-flops;
B. parallel scan paths that include:
a scan input for receiving test stimulus data to be applied to the combinational logic,
combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic,
a scan output for transmitting test response data obtained from the combinational logic, and
control inputs having an enable input and a select input for operating the parallel scan paths,
each scan path including functional flip-flops of the combinational logic that, in a test mode, are connected in series;
C. compare circuitry including: a response data input coupled to the scan output to receive the test response data from the group of scan paths, an expected data input to receive expected data, and a fail flag output, the compare circuitry indicating the result of a comparison of the received test response data and the expected data at the fail flag output; and
D. one of the scan paths including a scan cell having an input coupled to the fail flag output.
2. The circuit claim 1 in which the compare circuitry includes a mask data input for receiving mask data, the compare circuitry using the mask data to mask comparisons between selected ones of the test response data and expected data.
3. The circuit of claim 1 in which the compare circuitry includes a serial scan path routed through the compare circuitry, the serial scan path including scan cells for loading and shifting out the results of individual compare operations taking place between the response data and expected data.
4. The circuit of claim 1 in which for each scan path there is one scan data input, plural combinational connections, one scan output, one expected data input from the expected data bus, and one mask data input from a mask bus, which is connected to the compare circuitry.