Electronic interconnects and devices with topological surface states and methods for fabricating same
An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.
1. An interconnect comprising a material that is purified and crystalized to form an essentially insulating bulk portion having topological surface states occupied with charge carriers, the charge carriers having a spin vector and a momentum vector that are locked in a perpendicular relationship, the topological surface states and the essentially insulating bulk portion each having an electrical mobility, the electrical mobility of the topological surface states being at least 12 times greater than the electrical mobility of the essentially insulating bulk portion.
2. The interconnect of claim 1 , wherein the material has a mobility for the charge carriers of at least 9000 centimeter-squared per volt-second (cm 2 /V-s).
3. The interconnect of claim 1 , wherein the material comprises a non-stoichiometric material.
4. The interconnect of claim 1 , wherein the material comprises an element from column 15 of the periodic table.
5. The interconnect of claim 1 , wherein the material comprises an element from column 16 of the periodic table.
6. The interconnect of claim 1 , wherein the material comprises an element from column 13 of the periodic table.
7. The interconnect of claim 1 , wherein the material comprises an element from column 14 of the periodic table.
8. The interconnect of claim 1 , wherein the material comprises a solid solution alloy.
9. The interconnect of claim 1 , wherein the material has an atomic composition Bi 1-x Sb x , where 0.07≦x≦1.
10. The interconnect of claim 1 , wherein the material has an atomic composition Bi (2-2x) Sb 2x Se (3-3y) Te 3y where 0≦x≦1 and 0≦y≦1.
11. The interconnect of claim 1 , wherein the material has an atomic composition TlBiSe 2-2x Te 2x , where 0≦x≦1.
12. The interconnect of claim 1 , wherein the material has an atomic composition TlSbSe 2-2x Te 2x , where 0≦x≦1.
13. The interconnect of claim 1 , wherein the material has an atomic composition GeBi 2 Te 4 .
14. The interconnect of claim 1 , wherein the material has an atomic composition GeBi 4 Te 7 .
15. The interconnect of claim 1 , wherein the material comprises a heavy metal half Heusler phase with 18 electrons per formula unit.
16. The interconnect of claim 1 , comprising LuPtSb.
17. The interconnect of claim 1 , wherein the material comprises an HgTe—CdTe layered structure.
18. The interconnect of claim 1 , wherein the material comprises domains of crystalline antimony, the domains configured to support current flow parallel to a [111] crystallographic surface.
19. An integrated circuit comprising:
a plurality of devices; and
an interconnect providing an electrically conducting path between devices, the interconnect comprising a material that is purified and crystalized to form an essentially insulating bulk portion having topological surface states occupied with charge carriers, the charge carriers having a spin vector and a momentum vector that are locked in a perpendicular relationship, the topological surface states and the essentially insulating bulk portion each having an electrical mobility, the electrical mobility of the topological surface states being at least 12 times greater than the electrical mobility of the essentially insulating bulk portion.
20. A gated electronic device, comprising:
a material that is purified and crystalized to form an essentially insulating bulk portion having topological surface states occupied with charge carriers, the charge carriers having a spin vector and a momentum vector that are locked in a perpendicular relationship, the topological surface states and the essentially insulating bulk portion each having an electrical mobility, the electrical mobility of the topological surface states being at least 12 times greater than the electrical mobility of the essentially insulating bulk portion;
an insulator situated on the material; and
a gate material situated on the insulator;
wherein applying a potential to the gate material modulates a current flowing in the topological surface states of the material.
21. The device of claim 20 , configured such that the applying of the potential to the gate material changes the proportion of charged carrier transport via the topological surface states relative to charged carrier transport via bulk states.