Variable resistance memory device and method of manufacturing the same
A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.
1. A method of manufacturing a variable resistance memory device, the method comprising:
forming a plurality of vertical transistors extending from a surface of a semiconductor substrate in a direction perpendicular to the length and the width of the semiconductor substrate, each of the plurality of vertical transistors including a pillar and a gate surrounding a lower portion of the pillar;
forming a first spacer and a second spacer on a side wall of the pillar;
forming an insulating layer between the plurality of vertical transistors;
defining a space by removing the second spacer and an upper portion of the insulating layer; and
providing a conductive material in the space to form a shunt gate.
2. The method of claim 1 , further comprising:
forming, between the shunt gates, a heating electrode on each of the vertical transistors; and
forming a variable resistive layer on the heating electrode.
3. The method of claim 1 , wherein the defining a space further comprises:
damaging the second spacer and the upper portion of the insulating layer; and
selectively removing the second spacer and the upper portion of the insulating layer.
4. The method of claim 3 , wherein the second spacer and the upper portion of the insulating layer are damaged via a tilted ion implantation process.
5. The method of claim 1 , further comprising:
depositing a conductive layer on the semiconductor substrate and the shunt gate;
patterning the conductive layer to form a shunt gate extension, connected to the shunt gate, in the space between the vertical transistors; and
forming a heating electrode and a variable resistive layer on each of vertical transistors at both sides of the shunt gate extension.
6. The method of claim 5 , further comprising:
forming an additional gate layer on the shunt gate; and
forming a variable resistive structure on each of the vertical transistors.
7. The method of claim 6 , wherein the forming the variable resistive structure includes:
forming a heating electrode on each of the vertical transistors; and
forming a variable resistive material layer on the heating electrode.