Semiconductor devices having hybrid capacitors and methods for fabricating the same
A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.
1. A method of fabricating a semiconductor device, the method comprising:
forming a mold stack on a substrate;
forming a capacitor lower electrode penetrating the mold stack, the capacitor lower electrode being electrically connected to the substrate and having a hybrid structure including a solid shape and a shape comprising an opening therein;
patterning the mold stack to form a support pattern including an upper pattern and a lower pattern vertically spaced apart from the upper pattern, the upper pattern supporting an upper portion of the capacitor lower electrode, the lower pattern supporting a lower portion of the capacitor lower electrode, and the lower pattern having substantially the same planar shape as the upper pattern; and
sequentially forming a capacitor dielectric layer and a capacitor upper electrode on the capacitor lower electrode.
2. The method of claim 1 , wherein forming the capacitor lower electrode comprises:
forming a capacitor-hole penetrating the mold stack;
forming a first conductive layer filling the capacitor-hole and on the mold stack;
recessing the first conductive layer to form a first lower electrode filling a lower region of the capacitor-hole, the first lower electrode having the solid shape;
forming a second conductive layer extending along an inner sidewall of the capacitor-hole and covering the mold stack; and
patterning the second conductive layer to form a second lower electrode connected to the first lower electrode in an upper region of the capacitor-hole, the second lower electrode having the shape comprising an opening therein.
3. The method of claim 2 , wherein forming the mold stack comprises sequentially forming a lower mold layer, a lower support layer, an upper mold layer, and an upper support layer on the substrate,
wherein at least one of the upper support layer and the lower support layer has an etch selectivity with respect to at least one of the upper mold layer and the lower mold layer.
4. The method of claim 3 , wherein forming the support pattern comprises:
patterning the upper support layer to form the upper pattern on a sidewall of the second lower electrode and having an upper opening exposing a portion of the sidewall of the second lower electrode; and
etching the lower support layer using the upper pattern as an etch mask to form the lower pattern on a sidewall of the first lower electrode and having a lower opening exposing a portion of the sidewall of the first lower electrode.
5. The method of claim 4 , further comprising:
removing the upper mold layer by providing an etchant through the upper opening to form an upper space separating the upper pattern from the lower support layer; and
removing the lower mold layer by providing an etchant through the lower opening to form a lower space separating the lower pattern from the substrate.