IP Library Granted Patent US 9,337,135
Granted Patent B2
US 9,337,135 · App. 14/509,815 · Granted May 10, 2016

Pop joint through interposer

Inventors: Mirng-Ji Lii (Sinpu Township, TW); Chien-Hsun Lee (Chu-tung Town, TW); Yu-Min Liang (Zhongli, TW); Jiun Yi Wu (Zhongli, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/49833H01L23/49827H01L23/49838H01L24/81H01L25/0657H01L25/50H01L2224/81815H01L2225/06517H01L2225/06548H01L2225/06572H01L2924/14
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Quick Facts
Patent No.
US 9,337,135
App. No.
14/509,815
Granted
May 10, 2016
Kind
B2
Abstract

A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, with the first solder region in contact with a bottom end of the conductive pipe, and a through-opening in a center region of the interposer.

Claims (42)

1. A package comprising:

a package component comprising a first solder region; and

a first interposer over and bonded to the package component, wherein the first interposer comprises:

a core dielectric material;

a conductive pipe penetrating through the core dielectric material, wherein the first solder region is in contact with a bottom end of the conductive pipe; and

a through-opening in a center region of the first interposer.

2. The package of claim 1 further comprising a device die bonded to the package component, wherein the device die extends into the through-opening of the first interposer.

3. The package of claim 1 further comprising a second solder region in contact with a top end of the conductive pipe.

4. The package of claim 3 , wherein the first solder region and the second solder region are spaced apart from each other, with an unoccupied gap between the first solder region and the second solder region.

5. The package of claim 1 , wherein the first solder region extends into the conductive pipe.

6. The package of claim 1 further comprising a second interposer over the first interposer, wherein the second interposer comprises:

a plurality of metal pads distributed substantially uniformly throughout a top surface of the second interposer; and

a plurality of solder regions distributed in peripheral regions of a bottom surface of the second interposer, wherein no solder region is distributed to a center region of the bottom surface of the second interposer, and the plurality of solder regions is electrically coupled to the plurality of metal pads.

7. The package of claim 1 , wherein the conductive pipe further comprises a wing contacting an upper surface or a bottom surface of the core dielectric material.

8. A package comprising:

a first interposer comprising:

a core dielectric material;

a through-opening in a center region of the first interposer;

a plurality of conductive pipes penetrating through the core dielectric material, wherein the plurality of conductive pipes encircles the through-opening; and

a second interposer over the first interposer, the second interposer comprising:

a first plurality of solder regions on a bottom side of the second interposer, each bonded to one of the plurality of conductive pipes; and

a second plurality of solder regions on a top side of the second interposer.

9. The package of claim 8 further comprising a package over and bonded to the second plurality of solder regions.

10. The package of claim 8 further comprising a device die extending into the through-opening of the first interposer.

11. The package of claim 8 further comprising a package substrate underlying the first interposer, wherein the package substrate comprises a third plurality of solder regions, each bonded to one of the plurality of conductive pipes.

12. The package of claim 11 , wherein the first plurality of solder regions and the third plurality of solder regions extend into the plurality of conductive pipes, and the first plurality of solder regions is spaced apart from respective ones of the third plurality of solder regions by gaps.

13. The package of claim 8 , wherein the first plurality of solder regions extends into a plurality of through-openings in the first interposer, with each of the plurality of through-openings encircled by one of the plurality of conductive pipes.

14. The package of claim 8 , wherein the second plurality of solder regions is distributed substantially uniformly throughout the top side of the second interposer.

15. A package comprising:

a first interposer comprising:

a plurality of conductive pipes; and

an opening encircled by the plurality of conductive pipes;

a first plurality of solder regions extending into spaces in the plurality of conductive pipes, wherein the first plurality of solder regions comprises portions over the first interposer;

a second plurality of solder regions extending into the spaces in the plurality of conductive pipes, wherein the second plurality of solder regions comprises portions underlying the first interposer; and

a device die extending into the opening of the first interposer.

16. The package of claim 15 , wherein a first one of the first plurality of solder regions and a second one of the second plurality of solder regions extend into a same one of the plurality of conductive pipes, and are spaced apart from each other by an air gap.

17. The package of claim 15 , wherein the opening of the first interposer is a through-opening.

18. The package of claim 15 further comprising a second interposer overlapping the first interposer and the device die, wherein the second interposer comprises:

first conductive features bonded to the second plurality of solder regions and having a first pitch; and

second conductive features on an opposite side of the second interposer, wherein the second conductive features have a second pitch greater than the first pitch.

19. The package of claim 15 further comprising a package substrate, with the first plurality of solder regions and the device die both bonded to the package substrate.

20. The package of claim 15 further comprising an underfill filling the opening of the first interposer and gaps between the second plurality of solder regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2014
From: LII, MIRNG-JI; LEE, CHIEN-HSUN; LIANG, YU-MIN; WU, JIUN YI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 033915/0014 →
Continuity (1)
Related Publication 20160104668A1 · Apr 14, 2016