IP Library › Granted Patent US 9,337,279
Granted Patent B2
US 9,337,279 · App. 14/195,041 · Granted May 10, 2016

Group III-nitride-based enhancement mode transistor

Inventors: Clemens Ostermaier (Villach, AT); Gerhard Prechtl (St. Jacob i. Rosental, AT); Oliver Häberlen (Villach, AT)
Assignee: Infineon Technologies Austria AG
H01L29/205H01L29/0649H01L29/2003H01L29/207H01L29/402H01L29/41791H01L29/785
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Quick Facts
Patent No.
US 9,337,279
App. No.
14/195,041
Granted
May 10, 2016
Kind
B2
Abstract

A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer.

Claims (28)

1. A Group III-nitride-based enhancement mode transistor, comprising:

a multi-heterojunction fin structure, wherein a first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer;

an insulated gate electrode arranged on a second side face of the multi-heterojunction fin structure; and

a depletion electrode arranged on the p-type Group III-nitride layer.

2. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the multi-heterojunction fin structure comprises a multi-layer stack configured to provide channels of alternating conductivity types.

3. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein neighbouring heterojunctions of a fin of the multi-heterojunction fin structure are configured to provide channels supporting opposing charge carrier types.

4. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the depletion electrode is coupled to a source.

5. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the depletion electrode is electrically coupled to the p-type Group III-nitride layer and to channels of a second conductivity type, and wherein the insulated gate electrode is electrically coupled to channels of a first conductivity type, the second conductivity type opposing the first conductivity type.

6. The Group III-nitride-based enhancement mode transistor according to claim 1 , further comprising a further p-type Group III-nitride layer arranged on a second side face of a further fin of the multi-heterojunction fin structure, a first gate electrode portion arranged on the p-type Group III-nitride layer and a second gate electrode portion arranged on the further p-type Group III-nitride layer.

7. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the multi-heterojunction fin structure comprises a first Group III-nitride semiconductor layer arranged on a second Group III-nitride semiconductor layer forming a first heterojunction configured to provide a channel of a first conductivity type and a third Group III-nitride layer arranged on the second Group III-nitride semiconductor layer forming a second heterojunction configured to provide a channel of a second conductivity type, the second conductivity type opposing the first conductivity type.

8. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the multi-heterojunction fin structure is deposited on a substrate.

9. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the multi-heterojunction fin structure comprises mesa structures in a substrate.

10. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the p-type Group III-nitride layer is formed by Magnesium doping.

11. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the multi-heterojunction fin structure comprises a plurality of fins.

12. The Group III-nitride-based enhancement mode transistor according to claim 1 , further comprising a further p-type Group III-nitride layer arranged on a side face of a further multi-heterojunction fin structure arranged between the first multi-heterojunction fin structure and a drain electrode.

13. The Group III-nitride-based enhancement mode transistor according to claim 12 , wherein the further p-type Group III nitride layer is electrically coupled to a source electrode.

14. The Group III-nitride-based enhancement mode transistor according to claim 13 , further comprising a field plate structure electrically coupled to the further p-type Group III nitride layer and to the source electrode.

15. The Group III-nitride-based enhancement mode transistor according to claim 1 , wherein the multi-heterojunction fin structure comprises a plurality of trenches, wherein neighbouring trenches define a fin.

16. The Group III-nitride-based enhancement mode transistor according to claim 15 , wherein the trenches are arranged in a row and the insulated gate electrode is arranged in alternating ones of the trenches.

17. The Group III-nitride-based enhancement mode transistor according to claim 16 , wherein the alternating ones of the trenches are lined with an insulation layer.

18. The Group III-nitride-based enhancement mode transistor according to claim 15 , wherein the trenches are arranged in a row and a depletion electrode is arranged in alternating ones of the trenches.

19. A Group III-nitride-based enhancement mode transistor, comprising:

a multi-heterojunction fin structure, wherein a first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer;

a depletion electrode electrically coupled to the p-type Group III-nitride layer and to channels of a second conductivity type; and

an insulated gate electrode electrically coupled to channels of a first conductivity type, the second conductivity type opposing the first conductivity type.

20. The Group III-nitride-based enhancement mode transistor according to claim 19 , wherein the multi-heterojunction fin structure comprises a multi-layer stack configured to provide the channels of the first and second conductivity types.

21. The Group III-nitride-based enhancement mode transistor according to claim 19 , wherein neighbouring heterojunctions of a fin of the multi-heterojunction fin structure are configured to provide the channels of the first and second conductivity types.

22. The Group III-nitride-based enhancement mode transistor according to claim 19 , wherein the multi-heterojunction fin structure comprises a first Group III-nitride semiconductor layer arranged on a second Group III-nitride semiconductor layer forming a first heterojunction configured to provide a channel of the first conductivity type and a third Group III-nitride layer arranged on the second Group III-nitride semiconductor layer forming a second heterojunction configured to provide a channel of the second conductivity type.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2014
From: OSTERMAIER, CLEMENS; PRECHTL, GERHARD; HÄBERLEN, OLIVER
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 032379/0400 →
Continuity (1)
Related Publication 20150249134A1 · Sep 3, 2015