Method of making semiconductor device
A method of fabricating a semiconductor device includes epitaxially-growing a strained material in a cavity of a substrate comprising a major surface and the cavity, the cavity being below the major surface. A lattice constant of the strained material is different from a lattice constant of the substrate. The method also includes forming a first metal layer over the strained material, and forming a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm. The method further includes forming a dummy poly-silicon over the dielectric layer, and forming an interlayered dielectric layer (ILD) surrounding the dummy poly-silicon. The method additionally includes removing the dummy poly-silicon over the dielectric layer, and forming a second metal layer over the dielectric layer.
1. A method of fabricating a semiconductor device, comprising:
epitaxially-growing a strained material in a cavity of a substrate comprising a major surface and the cavity, the cavity being below the major surface, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
forming a first metal layer over the strained material;
forming a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm;
forming a dummy poly-silicon over the dielectric layer;
forming an interlayered dielectric layer (ILD) surrounding the dummy poly-silicon;
removing the dummy poly-silicon over the dielectric layer; and
forming a second metal layer over the dielectric layer.
2. The method of claim 1 , further comprising:
forming a shallow trench isolation (STI) region within the substrate;
forming a gate stack on the major surface of the substrate, wherein the STI region is disposed on one side of the gate stack;
forming the cavity distributed between the gate stack and the STI region.
3. The method of claim 1 , wherein the step of forming a first metal layer over the strained material is performed by CVD, ALD, or sputtering.
4. The method of claim 1 , wherein the step of forming a dielectric layer over the first metal layer is performed by CVD, ALD or sputtering.
5. The method of claim 1 , wherein epitaxially-growing the strained material comprises growing the strained material extending upward over the major surface of the substrate.
6. The method of claim 1 , wherein epitaxially-growing the strained material comprises epitaxially-growing the strained material comprising SiGe, SiC, or SiP.
7. The method of claim 1 , wherein forming the first metal layer comprises forming the first metal layer comprising TiN or TaN.
8. The method of claim 1 , wherein forming the dielectric layer comprises forming the dielectric layer comprising TiO 2 .
9. The method of claim 1 , wherein forming the dielectric layer comprises forming the dielectric layer comprising Al 2 O 3 , NiO, or HfO 2 .
10. The method of claim 1 , wherein forming the second metal layer comprises forming the second metal layer comprising Al, Ni, NiPt, or Pt.
11. A method of fabricating a semiconductor device, the method comprising:
epitaxially-growing a strained material in a cavity of a substrate comprising a major surface, the cavity being below the major surface, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
forming a gate stack over the substrate;
depositing a first metal layer over the strained material and the gate stack;
forming a dielectric layer over the first metal layer and the gate stack, wherein the dielectric layer has a thickness ranging from about 1 nanometers (nm) to about 10 nm;
depositing poly-silicon over the dielectric layer; and
forming an interlayered dielectric layer (ILD) surrounding the poly-silicon.
12. The method of claim 11 , wherein depositing the first metal layer comprises forming the metal layer continuously over the strained material and the gate stack.
13. The method of claim 11 , wherein forming the dielectric layer comprises forming the dielectric layer conformally over the gate stack and the strained material.
14. The method of claim 11 , further comprising etching the first metal layer and the dielectric layer using the poly-silicon as a mask.
15. The method of claim 11 , further comprising:
removing the poly-silicon over the dielectric layer; and
forming a second metal layer over the dielectric layer.
16. The method of claim 11 , further comprising planarizing the ILD, the gate stack and the poly-silicon.
17. A method of fabricating a semiconductor device, comprising:
epitaxially-growing a strained material in a cavity of a substrate comprising a major surface, the cavity being below the major surface, wherein a lattice constant of the strained material is different from a lattice constant of the substrate;
forming a shallow trench isolation (STI) region within the substrate;
forming a gate stack on the major surface of the substrate, wherein the cavity is between the gate stack and the STI region
depositing a first metal layer over the strained material, the gate stack and the STI; and
depositing a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm;
patterning the first metal layer and the dielectric layer using a poly-silicon hard mask; and
depositing an inter-layer dielectric (ILD) around the patterned first metal layer and the patterned dielectric layer.
18. The method of claim 17 , further comprising simultaneously removing the poly-silicon hard mask and a dummy electrode of the gate stack.
19. The method of claim 18 , further comprising simultaneously depositing a second metal in the gate stack and over the dielectric layer.