IP Library Granted Patent US 9,341,908
Granted Patent B2
US 9,341,908 · App. 14/263,012 · Granted May 17, 2016

Liquid crystal display device

Inventor: Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/1368G02F1/13624G09G3/342G09G3/3648H01L27/124H01L29/78651H01L33/0041G09G2300/0486G09G2300/0814G09G2300/0885G09G2320/066G09G2320/068G09G2320/106G09G2340/0435G09G2360/145H01L2924/0002
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Quick Facts
Patent No.
US 9,341,908
App. No.
14/263,012
Granted
May 17, 2016
Kind
B2
Abstract

It is an object to provide a liquid crystal display device which has excellent viewing angle characteristics and higher quality. The present invention has a pixel including a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.

Claims (30)

1. A semiconductor device comprising a first sub-pixel and a second sub-pixel, the semiconductor device comprising:

a first line;

a second line crossing the first line;

a first thin film transistor wherein a gate of the first thin film transistor is electrically connected to the first line, one of a source and a drain of the first thin film transistor is electrically connected to the second line;

a first pixel electrode of the first sub-pixel, wherein the first pixel electrode is electrically connected to the other of the source and the drain of the first thin film transistor;

a first capacitor wherein a first electrode of the first capacitor is electrically connected to the first pixel electrode;

a second thin film transistor wherein a gate of the second thin film transistor is electrically connected to the first line, one of a source and a drain of the second thin film transistor is electrically connected to the second line;

a second pixel electrode of the second sub-pixel, wherein the second pixel electrode is electrically connected to the other of the source and the drain of the second thin film transistor;

a second capacitor wherein a first electrode of the second capacitor is electrically connected to the second pixel electrode;

a switch wherein the one of the source and the drain of the first thin film transistor is electrically connected to the second line through the switch; and

a third pixel electrode wherein the third pixel electrode is electrically connected to the one of the source and the drain of the first thin film transistor,

wherein the first sub-pixel is located on a first side of the first line and the second sub-pixel is located on a second side of the first line, the first side being opposite to the second side, and

wherein each of the first thin film transistor and the second thin film transistor comprises a channel which comprises indium, zinc and oxygen.

2. The semiconductor device according to claim 1 , wherein the semiconductor device is a display device.

3. A module comprising:

a circuit board; and

a display panel electrically connected to the circuit board, the display panel comprising, a first sub-pixel and a second sub-pixel, the display device comprising:

a first line;

a second line crossing the first line;

a first thin film transistor wherein a gate of the first thin film transistor is electrically connected to the first line, one of a source and a drain of the drain of the first thin film transistor is electrically connected to the second line;

a first pixel electrode of the first sub-pixel, wherein the first pixel electrode is electrically connected to the other of the source and the drain of the first thin film transistor;

a first capacitor wherein a first electrode of the first capacitor is electrically connected to the first pixel electrode;

a second thin film transistor wherein a gate of the second thin film transistor is electrically connected to the first line, one of a source and a drain of the second thin film transistor is electrically connected to the second line;

a second pixel electrode of the sub-pixel, wherein the second pixel electrode is electrically connected to the other of the source and the drain of the second thin film transistor;

a second capacitor wherein a first electrode of the second capacitor is electrically connected to the second pixel electrode;

a switch wherein the one of the source and the drain of the first thin film transistor is electrically connected to the second line through the switch; and

a third pixel electrode wherein the third pixel electrode is electrically connected to the one of the source and the drain of the first thin film transistor,

wherein the first sub-pixel is located on a first side of the first line and the second sub-pixel is located on a second side of the first line, the first side being opposite to the second side, and

wherein each of the first thin film transistor and the second thin film transistor comprises a channel which comprises indium, zinc and oxygen.

4. The semiconductor device according to claim 3 , wherein the semiconductor device is a display device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2014
From: KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 033283/0220 →
Priority Claims (1)
JP 2007-132172 · May 17, 2007 · national
Continuity (5)
Division 13793427 · Mar 11, 2013
Continuation 13399147 · Feb 17, 2012
Continuation 13174842 · Jul 1, 2011
Division 12118982 · May 12, 2008
Related Publication 20140231807A1 · Aug 21, 2014