Packages with stacked dies and methods of forming the same

1. A method comprising:

bonding a first plurality of device dies onto a wafer, wherein the wafer comprises a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies;

sawing the wafer to form a die stack, wherein the die stack comprises a first device die from the first plurality of device dies and a second device die from the second plurality of device dies; and

bonding the die stack to a package substrate.

2. The method of claim 1 further comprising:

bonding a third device die to the package substrate, wherein the bonding the die stack is performed after the bonding the third device die to the package substrate, and wherein a die in the die stack is bonded to the third device die.

3. The method of claim 1 , wherein integrated circuits in the first device die and the second device die are identical to each other.

4. The method of claim 3 , wherein after the sawing, the second device die has an area greater than an area of the first device die.

5. The method of claim 1 further comprising:

attaching a metal lid onto the package substrate; and

dispensing a Thermal Interface Material (TIM) to join a die in the die stack to the metal lid.

6. The method of claim 1 further comprising:

bonding a third plurality of device dies over the first plurality of device dies, with each of the third plurality of device dies bonded to one of the first plurality of device dies, wherein the first plurality of device dies and the third plurality of device dies have identical structures.

7. The method of claim 6 further comprising:

dispensing an underfill into a gap between the first device die and the second device die, wherein at a time the third plurality of device dies is bonded, one of the third plurality of device dies is over a combination of the first device die and the underfill; and

curing the underfill.

8. A method comprising:

bonding a first plurality of device dies onto a wafer, wherein the wafer comprises a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies;

bonding a third plurality of device dies onto the first plurality of device dies, with each of the third plurality of device dies bonded to one of the first plurality of device dies, wherein the third plurality of device dies is identical to the first plurality of device dies;

sawing the wafer to form a plurality of die stacks, wherein each of the plurality of die stacks comprises a first device die from the first plurality of device dies, a second device die from the second plurality of device dies, and a third device die from the third plurality of device dies;

bonding an additional device die onto a package substrate; and

after the bonding the additional device die onto the package substrate, bonding one of the plurality of die stacks onto the additional device die.

9. The method of claim 8 , wherein after the bonding the one of the plurality of die stacks to the additional device die, the second device die in the one of the plurality of die stacks is bonded to the additional device die.

10. The method of claim 8 , wherein after the bonding the one of the plurality of die stacks to the additional device die, the second device die is a top die of the one of the plurality of die stacks.

11. The method of claim 8 further comprising:

attaching a metal lid onto the package substrate; and

dispensing a Thermal Interface Material (TIM) to join the plurality of die stacks to the metal lid.

12. The method of claim 8 , wherein the first plurality of device dies comprises integrated circuits identical to integrated circuits in the second plurality of device dies, and wherein in the plurality of die stacks, the second plurality of device dies has sizes greater than sizes of the first plurality of device dies.

13. The method of claim 8 further comprising:

dispensing an underfill into gaps between the first plurality of device dies and the second plurality of device dies, wherein at a time the third plurality of device dies is bonded, the third device dies is over the underfill; and

curing the underfill.

14. The method of claim 8 , wherein the first plurality of device dies, the second plurality of device dies, and the third plurality of device dies are memory dies, and wherein the additional device die is a logic device die.

15. A method comprising:

bonding a first device die and a second device die with a third device die and a fourth device die, respectively, wherein the first device die and the second device die are parts of an unsawed wafer;

dispensing a first underfill between the first device die and the third device die, and between the second device die and the fourth device die;

bonding a fifth device die and a sixth device die to the third device die and the fourth device die, respectively, wherein at a time the fifth device die and the sixth device die are bonded, the fifth device die and the sixth device die are overlying the first underfill;

dispensing a second underfill between the third device die and the fifth device die, and between the fourth device die and the sixth device die; and

sawing the unsawed wafer to separate a plurality of die stacks from each other, wherein the first device die, the third device die, the fifth device die, a portion of the first underfill, and a portion of the second underfill are in one of the plurality of die stacks.

16. The method of claim 15 further comprising:

bonding an additional device die onto a package substrate; and

after the bonding the additional device die onto the package substrate, bonding the one of the plurality of die stacks onto the additional device die.

17. The method of claim 15 , wherein after the first underfill is dispensed, a gap between the third device die and the fourth device die is unfilled with the first underfill.

18. The method of claim 15 , wherein the first underfill is dispensed before the fifth device die is bonded to the third device die, and the first underfill and the second underfill are dispensed in different process steps.

19. The method of claim 15 , wherein the first underfill and the second underfill are discrete underfill regions separated from each other.

20. The method of claim 8 , wherein the wafer comprises memory devices or logic devices therein.