Inverter circuit for an electric machine
An inverter circuit electrically connects between a high-voltage bus and a multi-phase electric machine, including a plurality of switch pairs. Each switch pair includes a first switch electrically connected in series with a second switch at a node. Each node electrically connects to a phase of the multi-phase electric machine with the first switch electrically connected between a positive side of the high-voltage bus and the node and the second switch electrically connected between a negative side of the high-voltage bus and the node. The first switch is configured as a normally-OFF switch. The second switch is configured as a normally-ON switch.
1. An inverter circuit electrically connected to a multi-phase electric machine, comprising:
a plurality of switch pairs, each switch pair including a first switch electrically connected in series with a second switch at a node, each node electrically connected to a phase of the multi-phase electric machine, the first switch of each of the switch pairs electrically connected between a positive high-voltage DC power bus and the node and the second switch of each of the switch pairs electrically connected between a negative high-voltage DC power bus and the node;
the first switch of each of the switch pairs being a cascode switch that is configured as a normally-OFF switch; and
the second switch of each of the switch pairs being configured as a normally-ON switch.
2. The inverter circuit of claim 1 , wherein each cascode switch includes a JFET switch electrically connected in series with a low-voltage pMOS switch, wherein the cascode switch converts to the normally-OFF configuration when the multi-phase electric machine is operating in an uncontrolled generator (UCG) mode.
3. The inverter circuit of claim 1 , wherein the second switch of each of the switch pairs comprises a JFET switch.
4. The inverter circuit of claim 1 , wherein the multi-phase electric machine is arranged in a star configuration.
5. The inverter circuit of claim 1 , wherein the multi-phase electric machine is arranged in a delta configuration.
6. An inverter circuit electrically connected between a high-voltage DC power bus and a multi-phase electric machine, comprising:
a plurality of switch pairs, each switch pair including a node electrically connected to a phase of the multi-phase electric machine;
each switch pair including a first switch electrically connected in series at the node with a second switch, wherein the first switch of each of the switch pairs electrically connects between a positive side of the high-voltage DC power bus and the node and the second switch of each of the switch pairs electrically connects between a negative side of the high-voltage DC power bus and the node;
a first gate drive circuit electrically operatively connected to each of the first switches and a second gate drive circuit electrically operatively connected to each of the second switches;
each of the first switches conducting electrical current only when activated by a first gate drive; and
each of the second switches conducting electrical current unless deactivated by a second gate drive.
7. The inverter circuit of claim 6 , wherein each of the first switches comprises an IGBT switch.
8. The inverter circuit of claim 6 , wherein each of the first switches comprises a cascode switch.
9. The inverter circuit of claim 8 , wherein each of the first switches includes a JFET switch electrically connected in series with a low-voltage pMOS switch.
10. The inverter circuit of claim 6 , wherein each of the second switches comprises a JFET switch.
11. An inverter circuit electrically connected to a high-voltage DC power bus, comprising:
a plurality of switch pairs, each switch pair including a node;
each switch pair including a first switch electrically connected in series at the node with a second switch, wherein the first switch of each of the switch pairs electrically connects between a positive side of the high-voltage DC power bus and the node and the second switch of each of the switch pairs electrically connects between a negative side of the high-voltage DC power bus and the node;
a first gate drive circuit electrically operatively connected to each of the first switches and a second gate drive circuit electrically operatively connected to each of the second switches;
wherein each of the first switches is a normally-OFF switch; and
wherein each of the second switches is a normally-ON switch.
12. The inverter circuit of claim 11 , wherein each of the first switches includes an IGBT switch.
13. The inverter circuit of claim 11 , wherein each of the first switches includes a cascode switch.
14. The inverter circuit of claim 13 , wherein each of the first switches includes a JFET switch electrically connected in series with a low-voltage pMOS switch.
15. The inverter circuit of claim 11 , wherein each of the second switches includes a JFET switch.