Core switching acceleration in asymmetric multiprocessor system

1. A device comprising:

a code analyzer unit to determine one or more instructions called by a code segment;

a code instrumentation unit to

select a subset of a plurality of processing cores to execute the code segment, the plurality of processing cores comprising a first core to execute a first instruction set architecture and a second core to execute a second instruction set architecture, the selection being based at least in part on the one or more code segments being natively executable in the first instruction set architecture or the second instruction set architecture, and

form instrumented program code by modifying the code segment to include one or more control operations based on the selected subset of the plurality of processing cores, the one or more control operations comprising a core wakeup operation before a move program code operation to initiate migration of the code segment to the first core or the second core.

2. The device of claim 1 , wherein the one or more control operations are to pre-warm the particular core and make the particular core ready for execution.

3. The device of claim 1 , wherein the plurality of processing cores comprise an asymmetric multiprocessor system.

4. A processor comprising:

a first core to operate at a first maximum power consumption rate and a second core to operate at a second maximum power consumption rate which is less than the first maximum power consumption rate, wherein the first core is to implement a first instruction set architecture and the second core is to implement a second instruction set architecture; and

binary analysis logic to:

determine what instructions are called by one or more code segments within program code;

select which of the first core or the second core to assign the one or more code segments for execution, the selection based at least in part on the one or more code segments being natively executable in the first instruction set architecture or the second instruction set architecture; and

insert, at least partly in response to the selection, one or more control operations into the program code based at least in part on the selection to form instrumented program code, the insertion comprising placing a core wakeup operation before a move program code to initiate migration of the code segment to the first core or the second core.

5. The processor of claim 4 , the one or more control operations comprising commands to:

wake up the first core;

wakeup the second core;

move program code to the first core; and

move program code to the second core.

6. The processor of claim 4 , further comprising remap and migrate logic to migrate one or more code segments of the instrumented program code to the first core or the second core for execution based at least in part on the one or more control operations.

7. The processor of claim 4 , the logic to select which of the first core or the second core to assign the one or more code segments for execution being based at least in part upon receiving a change to a performance state of the first core.

8. The processor of claim 7 , wherein the change in the performance state comprises a transition from a first state to a second state lower than the first.

9. The processor of claim 4 , wherein the first core and the second core comprise an asymmetric multiprocessor system.

10. The processor of claim 9 , wherein the binary analysis logic further to migrate the one or more code segments between cores of the asymmetric multiprocessor system.

11. The processor of claim 4 , the logic to select which of the first core or the second core to assign the one or more code segments for execution being based at least in part upon power consumption of the first core or the second core to execute the one or more code segments.

12. A method comprising:

receiving, into a memory, program code for execution on a first processor or a second processor, wherein the first processor to accept a first instruction set architecture and the second processor to accept a second instruction set architecture;

detecting functions called by the program code stored in the memory;

selecting one or more portions of the program code to execute on a particular processor based at least in part upon the functions called, the selecting further select the particular processor such that the detected function called executes natively; and

inserting one or more control operations into the program code stored in the memory to form instrumented program code at least partly in response to the selection, the inserting further to place a processor wakeup operation before a move program code operation in the instrumented program code.

13. The method of claim 12 , wherein the one or more control operations wake the first processor or the second processor from a low power state.

14. The method of claim 12 , wherein the one or more control operations migrate the program code between the first processor and the second processor.

15. The method of claim 12 , wherein the processor wakeup operation before a move program code operation in the instrumented program code to pre-warm the particular processor and make the particular processor ready for execution.

16. The method of claim 12 , the inserting comprising adding a processor wakeup operation to the program code.

17. The method of claim 16 , the inserting further comprising adding a program code move operation after a pre-determined number of executed instructions.

18. The method of claim 12 ,

the selecting further comprising selecting the particular processor such that the program code executes with instruction-level parallelism.

19. The method of claim 12 , the selecting being based at least in part on power consumption of the functions called if executed by the first processor or the second processor.