Device disconnect detection
Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.
1. A Universal Serial Bus downstream port, comprising:
physical layer circuitry to be coupled to a first signal line and a second signal line;
logic to send packet data to an upstream port on the first signal line and the second signal line in Low-Speed or Full-Speed (LS/FS) mode;
logic to send an End-Of-Packet (EOP) signal from the downstream port to the upstream port following the sending of the packet data in LS/FS mode, wherein the EOP signal is to cause the upstream port to enter an LS/FS idle state, wherein the upstream port is to maintain the LS/FS idle state without device pull-up;
logic to receive a digital ping during the LS/FS idle state indicating presence of the upstream port; and
logic to declare device disconnect if the downstream port does not receive the digital ping from the upstream port for three consecutive frames and the downstream port has not received any packet from the upstream port.
2. The Universal Serial Bus downstream port of claim 1 , further comprising logic to periodically receive additional digital pings over a time interval that indicates continued upstream port presence.
3. The Universal Serial Bus downstream port of claim 1 , further comprising logic to declare device disconnect if the downstream port does not receive the digital ping from the upstream port within a time period.
4. The Universal Serial Bus downstream port of claim 1 , further comprising logic to declare device disconnect if the downstream port does not receive the digital ping from the upstream port for three consecutive frames.
5. The Universal Serial Bus downstream port of claim 1 , further comprising logic to send the EOP signal on the first signal line and to receive the digital ping from the upstream port on the second signal line.
6. The Universal Serial Bus downstream port of claim 1 , further comprising logic to hold both the first signal line and the second signal line to ground during the LS/FS idle state.
7. The Universal Serial Bus downstream port of claim 1 , wherein the downstream port is included in a chip disposed on a same motherboard as the upstream port.
8. The Universal Serial Bus downstream port of claim 1 , wherein the downstream port is a Universal Serial Bus host and/or the upstream port is a Universal Serial Bus device.
9. A Universal Serial Bus upstream port, comprising:
physical layer circuitry to be coupled to a first signal line and a second signal line; and
logic, upon entering a Low-Speed or Full-Speed (LS/FS) idle state, to send a digital ping to a downstream port on the first signal line and/or the second signal line to indicate upstream port presence during the LS/FS idle state, wherein the upstream port is to maintain the LS/FS idle state without device pull-up, and wherein the downstream port declares device disconnect if the downstream port does not receive the digital ping from the upstream port for three consecutive frames and the downstream port has not received any packet from the upstream port.
10. The Universal Serial Bus upstream port of claim 9 , further comprising logic to periodically send additional digital pings over a time interval that indicates continued upstream port presence.
11. The Universal Serial Bus upstream port of claim 10 , wherein a time separation between the additional digital pings is less than three frames.
12. The Universal Serial Bus upstream port of claim 9 , further comprising logic to receive an End-Of-Packet (EOP) signal from the downstream port on the first signal line and to send the digital ping to the downstream port on the second signal line.
13. The Universal Serial Bus upstream port of claim 9 , wherein the upstream port is included in a chip disposed on a same motherboard as the downstream port.
14. The Universal Serial Bus upstream port of claim 9 , further comprising logic, during a suspend state in a native mode, to power down a transmitter and refrain from sending the digital pings to the downstream port while still maintaining device presence.
15. The Universal Serial Bus upstream port of claim 9 , further comprising logic, during a suspend state when in a native mode, to refrain from reporting device disconnect.
16. The Universal Serial Bus upstream port of claim 13 , further comprising logic, during a suspend state, to power down a transmitter and refrain from sending the digital pings to the downstream port while still maintaining device presence.
17. A system comprising:
a Universal Serial Bus downstream port and a Universal Serial Bus upstream port;
the Universal Serial Bus downstream port comprising:
physical layer circuitry to be coupled to a first signal line and a second signal line;
logic to send packet data to the upstream port on the first signal line and the second signal line in Low-Speed or Full-Speed (LS/FS) mode;
logic to send an End-Of-Packet (EOP) signal from the downstream port to the upstream port following the sending of the packet data in LS/FS mode, wherein the EOP signal is to cause the upstream port to enter an LS/FS idle state, wherein the upstream port is to maintain the LS/FS idle state without device pull-up; and
logic to receive a digital ping indicating a presence of the upstream port during the LS/FS idle state; and
logic to declare device disconnect if the downstream port does not receive the digital ping from the upstream port for three consecutive frames and the downstream port has not received any packet from the upstream port; and
the Universal Serial Bus upstream port comprising:
physical layer circuitry to be coupled to the first signal line and the second signal line; and
logic, upon entering the LS/FS idle state, to send the digital ping to the downstream port on the first signal line and/or the second signal line to indicate upstream port presence.
18. The system of claim 17 , the downstream port further comprising logic to periodically receive additional digital pings over a time interval that indicates continued upstream port presence.
19. The system of claim 17 , the downstream port further comprising logic to declare device disconnect if the downstream port does not receive the digital ping from the upstream port within a time period.
20. The system of claim 17 , the downstream port further comprising logic to declare device disconnect if the downstream port does not receive the digital ping from the upstream port for three consecutive frames.
21. The system of claim 17 , the downstream port further comprising logic to send the EOP signal on the first signal line and to receive the digital ping from the upstream port on the second signal line.
22. The system of claim 17 , the downstream port further comprising logic to hold both the first signal line and the second signal line to ground during an idle state.
23. The system of claim 17 , wherein the downstream port is included in a chip disposed on a same motherboard as the upstream port.
24. The system of claim 17 , wherein the downstream port is a universal serial bus host and/or the upstream port is a Universal Serial Bus device.
25. The system of claim 17 , the upstream port further comprising logic to periodically send additional digital pings over a time interval that indicates continued upstream port presence.
26. The system of claim 25 , wherein a time separation between the additional digital pings is less than three frames.
27. The system of claim 17 , the upstream port further comprising logic to receive an End-Of-Packet (EOP) signal from the downstream port on the first signal line and to send the digital ping to the downstream port on the second signal line.
28. The system of claim 17 , wherein the upstream port is included in a chip disposed on a same motherboard as the downstream port.
29. The system of claim 17 , the upstream port further comprising logic, during a suspend state in a native mode, to power down a transmitter and refrain from sending the digital pings to the downstream port while still maintaining device presence.
30. The system of claim 17 , the upstream port further comprising logic, during a suspend state when in a native mode, to refrain from reporting device disconnect.
31. The system of claim 28 , the upstream port further comprising logic, during a suspend state, to power down a transmitter and refrain from sending the digital pings to the downstream port while still maintaining device presence.