Logic analyzer circuit for programmable logic device

1. A computer-implemented method comprising:

receiving a design for a programmable logic device (PLD), the design including a plurality of nodes;

modifying, via one or more hardware processors, the design to include

a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes;

an external memory interface for connecting the logic analyzer circuit to an external memory; and

a trace memory enable register configured to alter a rate and format of data written to and read from the external memory; and

outputting the design to configure the PLD.

2. The method of claim 1 , wherein:

the logic analyzer circuit is arranged to store signals from the selected nodes when the logic analyzer circuit is programmed into the PLD.

3. The method of claim 1 , wherein the external memory interface and the trace memory enable register may be disabled.

4. The method of claim 1 , comprising: modifying, via the one or more hardware processors, the design to include:

a plurality of selectable groups of trigger signals, wherein any one of the trigger signals can be connected to any one of the nodes;

and for each trigger signal, a trigger condition for the logic analyzer circuit.

5. The method of claim 4 , wherein a trigger signal corresponds to a capture signal, such that when the trigger condition of the trigger signal is satisfied, the capture signal is stored in memory.

6. The method of claim 4 , wherein a trigger signal corresponds to multiple capture signals.

7. A non-transitory, computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method, the method comprising:

receiving a design for a programmable logic device (PLD), the design including a plurality of nodes;

modifying the design to include

a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes;

an external memory interface which connects the logic analyzer circuit to an external memory; and

a trace memory enable register configured to alter the rate and format of the data written to and read from the external memory; and

outputting the design to configure the PLD.

8. The computer-readable medium of claim 7 , wherein:

the logic analyzer circuit is arranged to store signals from the selected nodes when the logic analyzer circuit is programmed into the PLD.

9. The computer-readable medium of claim 7 , wherein the external memory interface and the trace memory enable register may be disabled.

10. The computer-readable medium of claim 7 , wherein the method comprises: modifying the design to include:

a plurality of selectable groups of trigger signals, wherein any of the trigger signals can be connected to any one of the nodes; and

for each trigger signal, a trigger condition for the logic analyzer circuit.

11. The computer-readable medium of claim 10 , wherein a trigger signal corresponds to a capture signal, such that when the trigger condition of the trigger signal is satisfied, the capture signal is stored in memory.

12. The computer-readable medium of claim 10 , wherein a trigger signal corresponds to multiple capture signals.

13. A system comprising: one or more hardware processors; and a memory storing instructions that, when executed by the one or more hardware processors, cause the one or more hardware processors to perform a method, the method comprising:

receiving a design for a programmable logic device (PLD), the design including a plurality of nodes;

modifying the design to include

a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes;

an external memory interface which connects the logic analyzer circuit to an external memory; and

a trace memory enable register configured to alter the rate and format of the data written to and read from the external memory; and

outputting the design to configure the PLD.

14. The system of claim 13 , wherein:

the logic analyzer circuit is arranged to store signals from the selected nodes when the logic analyzer circuit is programmed into the PLD.

15. The computer-readable medium of claim 13 , wherein the external memory interface and the trace memory enable register may be disabled.

16. The system of claim 13 , wherein the method comprises: modifying the design to include:

a plurality of selectable groups of trigger signals, wherein any of the trigger signals can be connected to any one of the nodes; and

for each trigger signal, a trigger condition for the logic analyzer circuit.

17. The system of claim 16 , wherein a trigger signal corresponds to a capture signal, such that when the trigger condition of the trigger signal is satisfied, the capture signal is stored in memory.

18. The system of claim 16 , wherein a trigger signal corresponds to multiple capture signals.

19. A logic analyzer circuit programmed into a chip, comprising:

a capture signal group selector configured to select a group of capture signals from a plurality of selectable groups of capture signals corresponding to a plurality of nodes, based on a capture signal group selection input; and

a trigger signal group selector configured to select a group of trigger signals from a plurality of selectable groups of trigger signals corresponding to the plurality of nodes, based on a capture trigger group selection input; and

a trace memory enable register configured to alter the rate and format of the data written to and read from a memory that is external to the chip and configured to store one of the selected group of capture signals responsive to a condition of a corresponding one of the selected group of trigger signals being met.

20. The logic analyzer circuit of claim 19 , wherein the trace memory enable register may be disabled.