IP Library Granted Patent US 9,349,670
Granted Patent B2
US 9,349,670 · App. 14/451,192 · Granted May 24, 2016

Semiconductor die assemblies with heat sink and associated systems and methods

Inventors: Wei Zhou (Singapore, SG); Zhaohui Ma (Singapore, SG); Aibin Yu (Singapore, SG)
Assignee: Micron Technology, Inc.
H01L23/3738H01L21/4878H01L23/367H01L25/0657H01L25/50
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Quick Facts
Patent No.
US 9,349,670
App. No.
14/451,192
Granted
May 24, 2016
Kind
B2
Abstract

Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

Claims (33)

1. A semiconductor die assembly, comprising:

a stack of first semiconductor dies;

a mold material having a first portion surrounding at least a portion of the stack of first semiconductor dies, and a second portion extending beyond the stack of first semiconductor dies, wherein the second portion of the mold material defines an opening adjacent an outermost one of the first semiconductor dies; and

a heat sink including a second semiconductor die, wherein the second semiconductor die is positioned on the outermost one of the first semiconductor dies of the stack of first semiconductor dies and within the opening defined by the second portion of the mold material, and wherein the second semiconductor die has an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

2. The semiconductor die assembly of claim 1 wherein the second semiconductor die includes a silicon substrate.

3. The semiconductor die assembly of claim 1 wherein the heat transfer features are at least partially defined by a plurality of recesses in the second semiconductor die.

4. The semiconductor die assembly of claim 1 wherein the heat transfer features include fins.

5. The semiconductor die assembly of claim 4 wherein the fins are defined by a plurality of grooves in the second semiconductor die.

6. The semiconductor die assembly of claim 4 wherein the fins are defined by a plurality of projections.

7. The semiconductor die assembly of claim 1 wherein:

the second semiconductor die has a thickness t 1 ;

the heat transfer features extend a distance d 1 into the second semiconductor die; and

d 1 is approximately between about one-third and one-half of t 1 .

8. The semiconductor die assembly of claim 1 , further comprising a plurality of thermally conductive elements disposed between individual first semiconductor dies of the stack of first semiconductor dies.

9. The semiconductor die assembly of claim 1 wherein the stack of first semiconductor dies includes:

a logic die; and

a plurality of memory dies between the logic die and the heat sink.

10. The semiconductor die assembly of claim 9 wherein the heat sink does not contain logic circuitry nor memory circuitry.

11. The semiconductor die assembly of claim 1 wherein a portion of each of the heat transfer elements projects beyond the mold material.

12. The semiconductor die assembly of claim 1 wherein the heat transfer features include a plurality of fins defined by a plurality of grooves in the second semiconductor die, and wherein at least a portion of each of the grooves is recessed below the second portion of the mold material.

13. The semiconductor die assembly of claim 1 wherein a portion of the second semiconductor die extends beyond a footprint of the stack of first semiconductor dies.

14. A semiconductor die assembly, comprising:

a stack of first semiconductor dies having an outermost first die with an outer surface;

a mold material having a first portion adjacent the stack of first semiconductor dies and a second portion projecting from the first portion, wherein the first and second portions define a recess adjacent the outer surface of the outermost first die; and

a second semiconductor die on the outer surface of the outermost first die, wherein the second semiconductor die includes

an exposed surface,

a plurality of heat transfer features formed along the exposed surface, and

a peripheral portion that extends beyond a footprint of the outermost first die and into the recess of the mold material.

15. The semiconductor die assembly of claim 14 wherein:

the second portion of the mold material extends to a first height above the outermost first die;

the heat transfer features include a plurality of fins defined by a plurality of grooves in the second semiconductor die; and

the fins extend to a second height above the outermost first die that is equal to or greater than the first height.

16. The semiconductor die assembly of claim 14 wherein the second semiconductor die does not contain logic circuity nor memory circuity.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2014
From: ZHOU, WEI; MA, ZHAOHUI; YU, AIBIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033458/0745 →
Continuity (1)
Related Publication 20160035648A1 · Feb 4, 2016