3D NAND nonvolatile memory with staggered vertical gates

1. A memory device, comprising:

a plurality of stacks of conductive strips having a depth direction along which adjacent conductive strips in a same stack are separated by dielectric material;

a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, the plurality of word lines electrically coupled to a plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips, the plurality of word lines including a first word line and a second word line adjacent to each other; and

the plurality of vertical gate columns between the plurality of stacks of conductive strips, the plurality of vertical gate columns including a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line, the first set of vertical gate columns staggered relative to the second set of vertical gate columns,

wherein at a first position along the plurality of word lines, the first word line overlies a first dielectric region and overlies none of the first set of vertical gate columns, and the second word line overlies one of the second set of vertical gate columns, and

wherein at a second position along the plurality of word lines, the first word line overlies one of the first set of vertical gate columns, and the second word line overlies a second dielectric region and overlies none of the second set of vertical gate columns,

wherein the first dielectric region and the second dielectric region have thicknesses in the depth direction that exceed a combined thickness in the depth direction of at least two of the conductive strips in the same stack; and

control circuitry controlling the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips, and controlling nonvolatile memory operations.

2. The memory device of claim 1 , wherein the plurality of vertical gate columns has a first pitch greater than a second pitch of the plurality of word lines.

3. The memory device of claim 1 , wherein the first set of vertical gate columns is staggered relative to the second set of vertical gate columns, such that the first set of vertical gate columns is separated by a first set of gate column gaps along the first word line, the second set of vertical gate columns is separated by a second set of gate column gaps along the second word line, the first set of vertical gate columns adjacent to the second set of gate column gaps, the second set of vertical gate columns adjacent to the first set of gate column gaps.

4. The memory device of claim 1 , wherein the plurality of vertical gate columns have curved exterior surfaces.

5. The memory device of claim 1 , further comprising a plurality of curved charge storage layers surrounding the plurality of vertical gate columns.

6. The memory device of claim 5 , wherein adjacent stacks of the plurality of stacks are separated by a volume having a length, and the volume alternates along the length between (i) dielectric fill and (ii) one of the plurality of vertical gate columns surrounded by one of the plurality of curved charge storage layers.

7. The memory device of claim 1 , further comprising a plurality of flat charge storage layers on opposite sides of the plurality of vertical gate columns.

8. The memory device of claim 7 , wherein adjacent stacks of the plurality of stacks are separated by a volume having a length, and the volume alternates along the length between (i) dielectric fill and (ii) one of the plurality of vertical gate columns having flat charge storage layers on opposite sides of the plurality of vertical gate columns.

9. The memory device of claim 1 , wherein the control circuitry performs a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to another word line of the plurality of word lines adjacent to the selected one of the plurality of word lines.

10. The memory device of claim 1 , wherein the control circuitry performs a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to two word lines of the plurality of word lines adjacent to the selected one of the plurality of word lines on opposite sides of the selected one of the plurality of word lines.

11. A method, comprising:

forming a plurality of stacks of conductive strips having a depth dimension along which adjacent conductive strips in a same stack are separated by dielectric material, the plurality of stacks separated by a plurality of gaps;

forming a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, the plurality of word lines electrically coupled to a plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips, the plurality of word lines including a first word line and a second word line adjacent to each other;

forming the plurality of vertical gate columns between the plurality of stacks of conductive strips, the plurality of vertical gate columns including a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line, the first set of vertical gate columns staggered relative to the second set of vertical gate columns,

wherein at a first position along the plurality of word lines, the first word line overlies a first dielectric region and overlies none of the first set of vertical gate columns, and the second word line overlies one of the second set of vertical gate columns, and

wherein at a second position along the plurality of word lines, the first word line overlies one of the first set of vertical gate columns, and the second word line overlies a second dielectric region and overlies none of the second set of vertical gate columns,

wherein the first dielectric region and the second dielectric region have thicknesses in the depth direction that exceed a combined thickness in the depth direction of at least two of the conductive strips in the same stack; and

forming control circuitry controlling the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips and to control nonvolatile memory operations.

12. The method of claim 11 , wherein the plurality of vertical gate columns has a first pitch greater than a second pitch of the plurality of word lines.

13. The method of claim 11 , further comprising:

forming charge storage layers and gate material in the plurality of gaps;

etching the gate material to leave the plurality of vertical gate columns separated by a plurality of holes; and

forming dielectric in the plurality of holes.

14. The method of claim 11 , further comprising:

forming dielectric in the plurality of gaps;

etching the dielectric and pluralities of stacks of conductive strips to form cavities centered in the dielectric in between the stacks of conductive strips;

forming the plurality of vertical gate columns in the cavities.

15. The method of claim 11 , wherein the first set of vertical gate columns is staggered relative to the second set of vertical gate columns, such that the first set of vertical gate columns is separated by a first set of gate column gaps along the first word line, the second set of vertical gate columns is separated by a second set of gate column gaps along the second word line, the first set of vertical gate columns adjacent to the second set of gate column gaps, the second set of vertical gate columns adjacent to the first set of gate column gaps.

16. The method of claim 11 , wherein the plurality of vertical gate columns have curved exterior surfaces.

17. The method of claim 11 , further comprising a plurality of curved charge storage layers surrounding the plurality of vertical gate columns.

18. The method of claim 17 , wherein adjacent stacks of the plurality of stacks are separated by a volume having a length, and the volume alternates along the length between (i) dielectric fill and (ii) one of the plurality of vertical gate columns surrounded by one of the plurality of curved charge storage layers.

19. The method of claim 11 , further comprising a plurality of flat charge storage layers on opposite sides of the plurality of vertical gate columns.

20. The method of claim 19 , wherein adjacent stacks of the plurality of stacks are separated by a volume having a length, and the volume alternates along the length between (i) dielectric fill and (ii) one of the plurality of vertical gate columns having flat charge storage layers on opposite sides of the plurality of vertical gate columns.

21. The memory device of claim 11 , wherein the control circuitry performs a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to another word line of the plurality of word lines adjacent to the selected one of the plurality of word lines.

22. The memory device of claim 11 , wherein the control circuitry performs a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to two word lines of the plurality of word lines adjacent to the selected one of the plurality of word lines on opposite sides of the selected one of the plurality of word lines.