IP Library › Granted Patent US 9,354,648
Granted Patent B2
US 9,354,648 · App. 14/197,045 · Granted May 31, 2016

Constant-voltage circuit

Inventors: Hiroshi Yajima (Osaka, JP); Hideyuki Kihara (Kanagawa, JP); Takahiro Uehara (Kyoto, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
G05F1/573G05F1/575
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Quick Facts
Patent No.
US 9,354,648
App. No.
14/197,045
Granted
May 31, 2016
Kind
B2
Abstract

A constant-voltage circuit having an overcurrent protection circuit which includes: a first sense transistor, one main terminal connected to an input terminal of the constant-voltage circuit and a control terminal connected to a control terminal of an output transistor generates a current corresponding to an output current from the output transistor; a voltage level adjusting circuit configured to generate a voltage corresponding to a voltage of a main terminal of the output transistor at an output terminal side of the constant-voltage circuit by extracting a current that is not affected by a change in the output current from the output transistor, and adjust a voltage of another main terminal of the first sense transistor such that the adjusted voltage becomes equal to the generated voltage; and a protection circuit to control a control voltage applied from an error amplifier to the control terminal of the output transistor.

Claims (26)

1. A constant-voltage circuit comprising:

an output transistor including a pair of main terminals connected to input and output terminals of the constant-voltage circuit, respectively, the input terminal being a terminal to which an input voltage is applied, the output terminal being a terminal from which an output voltage is obtained;

an error amplifier configured to apply, to a control terminal of the output transistor, a control voltage corresponding to an error between a voltage corresponding to the output voltage of the output terminal and a reference voltage; and

an overcurrent protection circuit configured to cause the output transistor to be in a non-conductive state when the overcurrent protection circuit has detected that an output current from the output transistor is an overcurrent, wherein the overcurrent protection circuit includes:

a first sense transistor, a first terminal of which is connected to the input terminal and

a control terminal of which is connected to the control terminal of the output transistor;

a second sense transistor, a first main terminal of which is connected to the input terminal and a control terminal of which is connected to an output terminal of the error amplifier;

a voltage level adjusting circuit configured to adjust a voltage of a second main terminal of the first sense transistor;

a protection circuit configured to control the control voltage applied from the error amplifier to the control terminal of the output transistor, the protection circuit controlling the control voltage in accordance with a current generated by the first sense transistor,

the voltage level adjusting circuit includes:

a first transistor, a first main terminal of which is connected to the main terminal of the output transistor at the output terminal side and another main terminal and a control terminal of which are shorted to each other;

a current source element connected to the second main terminal of the first transistor;

a second transistor, a first main terminal of which is connected to a second main terminal of the second sense transistor and a control terminal of which is connected to the control terminal of the first transistor;

a third transistor, a first main terminal of which is connected to the second main terminal of the second sense transistor and another main terminal and a control terminal of which are shorted to each other;

a current mirror circuit configured such that a current flowing out of a second main terminal of the second transistor is an input current to the current mirror circuit, and a current flowing out of the second main terminal of the third transistor becomes a duplicate current, which is a duplicate of the input current; and

a fourth transistor, a first main terminal of which is connected to the second main terminal of the first sense transistor, another main terminal of which is connected to

an input terminal of the protection circuit, and a control terminal of which is connected to the control terminal of the third transistor.

2. The constant-voltage circuit according to claim 1 , wherein

an aspect ratio of the third transistor is set to be less than each of an aspect ratio of the second transistor and an aspect ratio of the fourth transistor.

3. The constant-voltage circuit according to claim 1 , wherein the current source element of the voltage level adjusting circuit is either a constant current source or a resistor.

4. The constant-voltage circuit according to claim 1 , wherein

the protection circuit includes:

a first current/voltage converter configured to convert the current generated by the first sense transistor into a first voltage;

a first switch whose conduction is controlled in accordance with the first voltage such that a current corresponding to the first voltage flows through the first switch;

a second current/voltage converter configured to convert the current flowing through the first switch into a second voltage; and

a second switch interposed between the input terminal and the control terminal of the output transistor, the second switch being configured such that conduction between the input terminal and the control terminal of the output transistor is controlled in accordance with the second voltage.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: YAJIMA, HIROSHI; KIHARA, HIDEYUKI; UEHARA, TAKAHIRO
To: PANASONIC CORPORATION
Reel/Frame 032970/0343 →
Priority Claims (1)
JP 2011-210913 · Sep 27, 2011 · national
Continuity (2)
Continuation PCTJP2012001639 · Mar 9, 2012
Related Publication 20140184182A1 · Jul 3, 2014