IP Library › Granted Patent US 9,355,697

Granted Patent B2

US 9,355,697 · App. 13/646,497 · Granted May 31, 2016

Wordline driver

Inventors: Adrian Earle (Kanata, CA); Atul Katoch (Kanata, CA)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

G11C8/08

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 9,355,697
App. No.: 13/646,497
Granted: May 31, 2016
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A circuit includes a first transistor and a second transistor of a first type. The circuit further includes a first transistor of a second type. A first first-type drain is coupled to a second first-type source. A first first-type source is configured to have a first voltage value. A first first-type gate is configured to have a first control signal. A second first-type drain is configured to serve as a wordline. A second first-type gate is configured to have a second voltage value. A first second-type source is configured to have a third voltage value. A first second-type gate is configured to have a second control signal. The first transistor and the second transistor of the first type are configured to provide the first voltage value for the wordline. The first transistor of the second-type is configured to provide the third voltage value the wordline.

Claims (180)

1. A circuit comprising:

a signal generation circuit;

a first transistor of a first type having a drain, a source, and a gate;

a second transistor of the first type having a drain, a source, and a gate; and

a first transistor of a second type having a drain, a source, and a gate,

wherein the circuit is configured to have

the drain of the first transistor of the first type coupled to the source of the second transistor of the first type;

a first voltage value at the source of the first transistor of the first type;

a first control signal at the gate of the first transistor of the first type;

the drain of the second transistor of the first type serve as a wordline

a third voltage value at the source of the first transistor of the second type;

a second control signal at the gate of the first transistor of the second type;

the first transistor of the first type and the second transistor of the first type provide the first voltage value for the wordline;

the first transistor of the second type provide the third voltage value for the wordline;

a same second voltage value at the gate of the second transistor of the first type when the wordline has the first voltage value and when the wordline has the third voltage value; and

the signal generation circuit generate the first control signal and the second control signal, the first control signal having a first logically high level when the second control signal has a second logically high level, the first control signal having a first logically low level when the second control signal has a second logically low level, the first logically high level being different from the second logically high level, and the first logically low level being different from the second logically low level.

2. The circuit of claim 1 , further comprising:

a second transistor of the second type having a drain, a source, and a gate,

wherein

the drain of the second transistor of the second type is coupled to the drain of the second transistor of the first type;

the source of the second transistor of the second type is coupled to the drain of the first transistor of the second type; and

the gate of the second transistor of the second type is coupled to the gate of the second transistor of the first type.

3. The circuit of claim 2 , wherein the signal generation circuit is configured to cause

the first control signal to switch between the first voltage value and the second voltage value; and

the second control signal to switch between the second voltage value and the third voltage value.

4. The circuit of claim 1 , wherein

the second voltage value differs from the first voltage value by an amount less than a transistor damaging voltage.

5. The circuit of claim 1 , wherein

the drain of the first transistor of the second type is coupled to the drain of the second transistor of the first type;

the signal generation circuit is configured to cause

the second control signal to switch between a fourth voltage value and the third voltage value; and

the first control signal to switch between the first voltage value and the second voltage value;

the first voltage value is higher than the fourth voltage value;

the fourth voltage value is higher than the second voltage value; and

the third voltage value has a negative voltage value.

6. The circuit of claim 5 , wherein the signal generation circuit comprises:

a third transistor of the first type having a drain, a source, and a gate; and

a third transistor of the second type having a drain, a source, and a gate,

wherein the signal generation circuit is configured to have

the second control signal at the source of the third transistor of the second type;

the drain of the third transistor of the second type coupled to the drain of the third transistor of the first type; and

the fourth voltage value at the source of the third transistor of the first type.

7. The circuit of claim 1 , wherein the signal generation circuit comprises:

a third transistor of the first type having a drain, a source, and a gate;

a fourth transistor of the first type having a drain, a source, and a gate; and

a fifth transistor of the first type having a drain, a source, and a gate,

wherein the signal generation circuit is configured to have

the first control signal at the drain of the third transistor of the first type;

the first voltage value at the source of the third transistor of the first type;

the drain of the fourth transistor of the first type coupled to the source of the fifth transistor of the first type;

the first voltage value at the source of the fourth transistor of the first type; and

the first control signal at the drain of the fifth transistor of the first type.

8. The circuit of claim 1 , wherein the signal generation circuit comprises:

a second transistor of the second type having a drain, a source, and a gate;

a third transistor of the second type having a drain, a source, and a gate; and

a fourth transistor of the second type having a drain, a source, and a gate,

wherein the signal generation circuit is configured to have

the first control signal at the drain of the second transistor of the second type;

the source of the second transistor of the second type coupled to the drain of the third transistor of the second type;

the source of the third transistor of the second type coupled to the drain of the fourth transistor of the second type; and

the second voltage value at the source of the fourth transistor of the second type.

9. The circuit of claim 8 , wherein the signal generation circuit comprises:

a fifth transistor of the second type having a drain, a source, and a gate,

wherein the signal generation circuit is configured to have

the drain of the fifth transistor of the second type coupled to the drain of the fourth transistor of the second type;

a voltage value at the source of the fifth transistor of the second type, the voltage value lesser than the second voltage value; and

a signal at the gate of the fifth transistor of the second type, the signal having a pulse width that defines the time the fifth transistor of the second type is turned on.

10. The circuit of claim 1 , wherein the signal generation circuit comprises:

a second transistor of the second type having a drain, a source, and a gate; and

a third transistor of the second type having a drain, a source, and a gate,

wherein the signal generation circuit is configured to have

the second control signal at the drain of the second transistor of the second type;

the source of the second transistor of the second type coupled to the drain of the third transistor of the second type; and

the third voltage value at the source of the third transistor of the second type.

11. The circuit of claim 10 , wherein the signal generation circuit is configured to have

a first gate signal at the gate of the second transistor of the second type, the first gate signal switching between the third voltage value and a fourth voltage value; and

a second gate signal at the gate of the third transistor of the second type, the second gate signal switching between the third voltage value and the fourth voltage value.

12. The circuit of claim 10 , wherein the signal generation circuit comprises:

a third transistor of the first type having a drain, a source, and a gate; and

a fourth transistor of the second type having a drain, a source, and a gate;

wherein the signal generation circuit is configured to have

the second control signal at the drain of the third transistor of the first type;

a fourth voltage value at the source of the third transistor of the first type;

the second control signal at the source of the fourth transistor of the second type; and

the fourth voltage value at the drain of the fourth transistor of the second type.

13. A circuit comprising:

a signal generation circuit;

a first transistor of a first type having a drain, a source, and a gate;

a second transistor of the first type having a drain, a source, and a gate;

a first transistor of a second type having a drain, a source, and a gate; and

a second transistor of the second type having a drain, a source, and a gate,

wherein the circuit is configured to have

the drain of the first transistor of the first type coupled to the source of the second transistor of the first type;

a first voltage value at the source of the first transistor of the first type;

a first control signal at the gate of the first transistor of the first type;

the drain of the second transistor of the first type coupled to the drain of the second transistor of the second type and configured to serve as a wordline;

the gate of the second transistor of the first type coupled to the gate of the second transistor of the second type and configured to have a second voltage value;

the source of the second transistor of the second type coupled to the drain of the first transistor of the second type;

a third voltage value at the source of the first transistor of the second type;

a second control signal at the gate of the first transistor of the second type; and

the signal generation circuit generate the first control signal and the second control signal,

the first control signal being at the first voltage value when the second control signal is at the second voltage value,

the first control signal being at the second voltage value when the second control signal is at the third voltage value, and

the second voltage value being unchanged for the first control signal being at the first voltage value and at the second voltage value.

14. The circuit of claim 13 , wherein the signal generation circuit comprises:

a first set of one or more transistors of the first type configured to provide the first voltage value to the first control signal;

a first set of one or more transistors of the second type configured to provide the second voltage value to the first control signal;

a second set of one or more transistors of the first type configured to provide the second voltage value to the second control signal; and

a second set of one or more transistors of the second type configured to provide the third voltage value to the second control signal.

15. The circuit of claim 14 , wherein

the first set of one or more transistors of the first type includes

a third transistor of the first type having a drain, a source, and a gate;

a fourth transistor of the first type having a drain, a source, and a gate; and

a fifth transistor of the first type having a drain, a source, and a gate;

the first set of one or more transistors of the second type includes

a third transistor of the second type having a drain, a source, and a gate;

a fourth transistor of the second type having a drain, a source, and a gate; and

a fifth transistor of the second type having a drain, a source, and a gate;

the second set of one or more transistors of the first type includes

a sixth transistor of the first type having a drain, a source, and a gate;

a seventh transistor of the first type having a drain, a source, and a gate; and

an eighth transistor of the first type having a drain, a source, and a gate; and

the second set of one or more transistors of the second type includes

a sixth transistor of the second type having a drain, a source, and a gate; and

a seventh transistor of the second type having a drain, a source, and a gate,

wherein the circuit is configured to have

the first control signal at the drain of the third transistor of the first type;

the first voltage value at the source of the third transistor of the first type;

the drain of the fourth transistor of the first type coupled to the source of the fifth transistor of the first type;

the first voltage value at the source of the fourth transistor of the first type;

the first control signal at the drain of the fifth transistor of the first type;

the first control signal at the drain of the third transistor of the second type;

the source of the third transistor of the second type coupled to the drain of the fourth transistor of the second type;

the source of the fourth transistor of the second type coupled to the drain of the fifth transistor of the second type;

the third voltage value at the source of the fifth transistor of the second type;

the second control signal at the drain of the sixth transistor of the first type;

the second voltage value at the source of the sixth transistor of the first type;

the drain of the seventh transistor of the first type coupled to the source of the eighth transistor of the first type;

the second voltage value at the source of the seventh transistor of the first type;

the second control signal at the drain of the eighth transistor of the first type;

the second control signal at the drain of the sixth transistor of the second type;

the source of the sixth transistor of the second type coupled to the drain of the seventh transistor of the second type; and

the third voltage value at the source of the seventh transistor of the second type.

16. The circuit of claim 15 , wherein the signal generation circuit comprises:

an eighth transistor of the second type having a drain, a source, and a gate;

a ninth transistor of the first type having a drain, a source, and a gate; and

a ninth transistor of the second type having a drain, a source, and a gate,

wherein the signal generation circuit is configured to have

the drain of the eighth transistor of the second type coupled to the drain of the fifth transistor of the second type;

the gate of the eighth transistor of the second type receive a gate signal having a pulse width that defines a time for the eighth transistor of the second type to be on;

the drain of the ninth transistor of the second type coupled to the drain of the ninth transistor of the first type; and

the second control signal at the source of the ninth transistor of the first type.

17. The circuit of claim 15 , wherein the circuit is configured to satisfy at least one of the following conditions:

a gate voltage applied to the gate of the sixth transistor of the second type is shifted compared with a gate voltage applied to the gate of the fourth transistor of the second type; and

a gate voltage applied to the gate of the seventh transistor of the second type is shifted compared with a gate voltage applied to the gate of the fifth transistor of the second type.

18. The circuit of claim 14 , wherein the circuit is configured to satisfy at least one of the following conditions:

a first assistant control circuit is coupled to the first set of one or more transistors of the second type and is configured to pull down the first control signal; and

a second assistant circuit is configured to have the second control signal and to pull up the second control signal.

19. A circuit comprising:

a signal generation circuit;

a first transistor of a first type having a drain, a source, and a gate;

a second transistor of the first type having a drain, a source, and a gate; and

a first transistor of a second type having a drain, a source, and a gate,

wherein the circuit is configured to have

the drain of the first transistor of the first type coupled to the source of the second transistor of the first type;

a first voltage value at the source of the first transistor of the first type;

a first control signal at the gate of the first transistor of the first type;

the drain of the second transistor of the first type serve as a wordline;

a second voltage value at the gate of the second transistor of the first type;

a third voltage value at the source of the first transistor of the second type;

a second control signal at the gate of the first transistor of the second type;

the signal generation circuit comprising:

at least one third transistor of the first type configured to provide the first voltage value to the first control signal;

at least one second transistor of the second type configured to provide the second voltage value to the first control signal;

at least one fourth transistor of the first type configured to provide the second voltage value to the second control signal; and

at least one third transistor of the second type configured to provide the third voltage value to the second control signal; and

the second voltage value is about half of an operational voltage value of the circuit.

20. The circuit of claim 19 , wherein

the first control signal is at the first voltage value when the second control signal is at the second voltage value, and

the first control signal is at the second voltage value when the second control signal is at the third voltage value.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2012

From: EARLE, ADRIAN; KATOCH, ATUL

To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Reel/Frame 029093/0355 →

Continuity (2)

Provisional Application 61581013 · Dec 28, 2011

Related Publication 20130170313A1 · Jul 4, 2013