IP Library › Granted Patent US 9,355,916
Granted Patent B2
US 9,355,916 · App. 14/668,103 · Granted May 31, 2016

Semiconductor manufacturing method and semiconductor device

Inventors: Daiyu Kondo (Atsugi, JP); Shintaro Sato (Atsugi, JP); Naoki Yokoyama (Machida, JP); Motonobu Sato (Isehara, JP)
Assignee: FUJITSU LIMITED
H01L21/823871H01L21/28525H01L21/28575H01L21/76877H01L21/76897H01L21/84H01L23/5226H01L23/53276H01L27/0922H01L27/1203H01L27/124H01L27/1259H01L29/16H01L29/201H01L29/78681H01L29/78684H01L21/8258
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Quick Facts
Patent No.
US 9,355,916
App. No.
14/668,103
Granted
May 31, 2016
Kind
B2
Abstract

A method manufactures a semiconductor device which allows nanocarbon materials, such as high-quality graphene and carbon nanotube to be used. The method of manufacturing the semiconductor device comprises forming on a substrate a wiring structure including wires of nanocarbon material; forming on the wiring structure an element structure including a semiconductor element; and interconnecting the wires of the wiring structure and the semiconductor element of the element structure.

Claims (50)

1. A method of manufacturing a semiconductor device, comprising:

forming on a substrate a wiring structure including wires of a nanocarbon material;

forming on the wiring structure an element structure including semiconductor elements; and

interconnecting the wires of the wiring structure and the semiconductor element of the element structure, wherein

the wiring structure includes plugs connected to the wires, the plugs of the wiring structure being formed of carbon nanotube, and

in the interconnecting, the plugs of the wiring structure and electrodes of the semiconductor element of the element structure are jointed.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein

the plugs of the wiring structure is formed of a metal.

3. A method of manufacturing a semiconductor device according to claim 1 , wherein

the wires of the nanocarbon material of the wiring structure is formed of graphene.

4. A method of manufacturing a semiconductor device, comprising:

forming a wiring structure including wires of a nanocarbon material;

forming on a substrate an element structure including a semiconductor element; and

transferring the wiring structure to the element structure formed on the substrate; and interconnecting the semiconductor element of the element structure and the wires of the wiring structure, wherein

the wiring structure includes plugs connected to the wires, the plugs of the wiring structure being formed of carbon nanotube, and

in the interconnecting, the plugs of the wiring structure and electrodes of the semiconductor element of the element structure are jointed.

5. A method of manufacturing a semiconductor device according to claim 4 , wherein

the plugs of the wiring structure is formed of a metal.

6. A method of manufacturing a semiconductor device according to claim 4 , wherein

the wires of the nanocarbon material of the wiring structure is formed of graphene.

7. A method of manufacturing a semiconductor device, comprising:

forming on a substrate a wiring structure including wires of a nanocarbon material;

forming on the wiring structure an element structure including semiconductor elements; and

interconnecting the wires of the wiring structure and the semiconductor element of the element structure, wherein

the semiconductor element of the element structure is a CMOS element including an n-TFT and a p-TFT, wherein

the n-TFT includes a channel of InGaAs, and a source electrode and a drain electrode of an alloy of Ge and a metal, and

the p-TFT includes a channel of Ge, and a source electrode and a drain electrode of an alloy of Ge and a metal.

8. A method of manufacturing a semiconductor device, comprising:

forming a wiring structure including wires of a nanocarbon material;

forming on a substrate an element structure including a semiconductor element; and

transferring the wiring structure to the element structure formed on the substrate; and interconnecting the semiconductor element of the element structure and the wires of the wiring structure, wherein

the semiconductor element of the element structure is a CMOS element including an n-TFT and a p-TFT, wherein

the n-TFT includes a channel of InGaAs, and a source electrode and a drain electrode of an alloy of Ge and a metal, and

the p-TFT includes a channel of Ge, and a source electrode and a drain electrode of an alloy of Ge and a metal.

9. A semiconductor device, comprising:

a wiring structure formed on a substrate and including wires of a nanocarbon material; and

an element structure formed on the wiring structure, the element structure including a semiconductor element,

the wires of the wiring structure and the semiconductor element of the element structure being interconnected, wherein

the wiring structure includes plugs connected to the wires, the plugs of the wiring structure being formed of carbon nanotube, and

in the interconnecting, the plugs of the wiring structure and electrodes of the semiconductor element of the element structure are jointed.

10. A semiconductor device according to claim 9 , wherein

the wiring structure includes plugs of carbon nanotube connected to the wires, and

the plugs of the wiring structure and electrodes of the semiconductor element of the element structure are jointed.

11. A semiconductor device, comprising:

a wiring structure formed on a substrate and including wires of a nanocarbon material; and

an element structure formed on the wiring structure, the element structure including a semiconductor element,

the wires of the wiring structure and the semiconductor element of the element structure being interconnected, wherein

the semiconductor element of the element structure is a CMOS element including an n-TFT and a p-TFT, wherein

the n-TFT includes a channel of InGaAs, and a source electrode and a drain electrode of an alloy of Ge and a metal, and

the p-TFT includes a channel of Ge, and a source electrode and a drain electrode of an alloy of Ge and a metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2015
From: KONDO, DAIYU; SATO, MOTONOBU; SATO, SHINTARO; YOKOYAMA, NAOKI
To: FUJITSU LIMITED
Reel/Frame 035759/0018 →
Priority Claims (1)
JP 2014-066349 · Mar 27, 2014 · national
Continuity (1)
Related Publication 20150279747A1 · Oct 1, 2015