Circuit and method for imprint reduction in FRAM memories
A method of operating a memory circuit (FIGS. 8 A and 8 B) is disclosed. The method includes writing true data (01) to a plurality of bits (B 0 , B 1 ). A first data state (0) is written to a signal bit (B i ) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.
1. A circuit, comprising:
a memory cell; and
a sense amplifier;
wherein the sense amplifier comprises:
two p-channel transistors in series arranged in a cross-coupled configuration with two n-channel transistors in series;
a first switching transistor coupled between the memory cell and a first common drain terminal of one of the p-channel transistors and one of the n-channel transistors; and
a first inverter having an input terminal coupled to the first common drain terminal and having an output terminal coupled to the memory cell.
2. A circuit as in claim 1 , wherein the memory cell is a one-transistor, one-capacitor (1T1C) memory cell.
3. A circuit as in claim 1 , wherein the memory cell is a two-transistor, two-capacitor (2T2C) memory cell.
4. A circuit as in claim 1 , comprising:
a second switching transistor coupled to a second common drain terminal of the other one of the p-channel transistors and other one of the n-channel transistors; and
a second inverter having an input terminal coupled to the second common drain terminal and having an output terminal coupled to the second switching transistor.
5. A circuit as in claim 1 , comprising:
a bit line coupled between the memory cell and the sense amplifier; and a word line coupled to the memory cell.
6. A circuit as in claim 1 , wherein the memory cell is a ferroelectric memory cell.
7. A circuit as in claim 1 , wherein the memory cell is one of a static random access memory (SRAM) cell, a magnetic random access memory (MRAM), and a resistive random access memory (RRAM) cell.
8. A system, comprising:
a processor circuit;
an input device coupled to the processor circuit;
an output device coupled to the processor circuit; and
a circuit comprising:
a memory cell;
a sense amplifier;
wherein the sense amplifier comprises:
two p-channel transistors in series arranged in a cross-coupled configuration with two n-channel transistors in series;
a first switching transistor coupled between the memory cell and a common drain terminal of one of the p-channel transistors and one of the n-channel transistors; and
an inverter having an input terminal coupled to the common drain terminal and having an output terminal coupled to the memory cell.
9. A system as in claim 8 , wherein the memory cell is a one-transistor, one-capacitor (1T1C) memory cell.
10. A system as in claim 8 , wherein the memory cell is a two-transistor, two-capacitor (2T2C) memory cell.
11. A system as in claim 8 , wherein the memory cell is a ferroelectric memory cell.