Group III nitride integration with CMOS technology
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.
1. A semiconductor structure comprising;
a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein said nFET device region and said pFET device region comprise a topmost silicon layer of said substrate, and wherein said Group III nitride device region comprises a <111> silicon layer of said substrate, a Group III nitride material base material having a first band gap located atop a surface of said <111> silicon layer, and a Group III nitride channel material having a second band gap located on a mesa portion of said Group III nitride base material, wherein said second band gap is different from said first band gap and wherein said Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of said topmost silicon layer, wherein a Group III nitride growth seed layer having a horizontal portion is located between said <111> silicon layer of said substrate and said Group III nitride base material, wherein said Group III nitride growth seed layer further comprises a vertical portion located on a sidewall surface of said Group III nitride base material.
2. The semiconductor structure of claim 1 , further comprising an nFET gate stack located on said topmost silicon layer in said nFET device region, a pFET gate stack located on said topmost silicon layer in said pFET device region, and a high electron mobility transistor gate stack located on said Group III nitride channel material in said Group III nitride device region.
3. The semiconductor structure of claim 1 , further comprising an insulator layer located beneath said topmost silicon layer in both said nFET device region and said pFET device region but not said Group III nitride device region, wherein said insulator layer is located on a portion of said <111> silicon layer.
4. The semiconductor structure of claim 1 , wherein said nFET device region is separated from said pFET device region by a trench isolation structure and wherein said pFET device region is separated from said Group III nitride device region by another trench isolation structure.
5. The semiconductor structure of claim 1 , further comprising a source/drain region located within each end portion of said Group III nitride channel material having said second band gap.
6. The semiconductor structure of claim 2 , further comprising a middle-of-the-line (MOL) dielectric material surrounding said nFET gate stack, said pFET gate stack and said high electron mobility transistor gate stack, wherein said MOL dielectric material contains metal contacts that extend to source/drain regions present at the footprint of each of said nFET gate stack, said pFET gate stack and said high electron mobility transistor gate stack.
7. The semiconductor structure of claim 1 , wherein Group III nitride base material has a thickness below 1.5 μm with a nominal patterned density of 50% or less.